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Showing posts with the label Verilog HDL

YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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Digital Design Engineer at Analog Devices

  Hello Dear Readers, Currently, at Analog Devices Bangalore vacancy for Digital Design Engineer role. Analog Devices is a global leader in the design and manufacturing of integrated circuits to help solve the toughest engineering challenges. Analog Devices enables our customers to interpret the world around us by intelligently bridging the physical and digital with unmatched technologies that sense, measure and connect. We create innovative solutions to solve design challenges in instrumentation, automation, communications, healthcare, automotive and numerous other industries. Analog Devices Inc (ADI) is looking for Digital IC Design and Verification Engineers for its Chip Design and development team in Bangalore, India. The selected students will work on chip development based on ultra-deep submicron semiconductor process technologies. They will be guided and trained by ADI’s experienced design and verification engineers. Responsibilities: Development of key digital blocks a...
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SoC Verification Engineer at Truechip

  Hello Dear Readers,   Currently, at Truechip vacancy for an SoC Verification Engineer role. Post: SoC Verification Engineer Required Experience: 1 to 3 years Location: Bangalore, Delhi NCR, Hyderabad Openings: 8-10 Education: BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Worked on IP level verification environment: 1 to 3 years of experience Good experience with Verilog, System Verilog and UVM Experience with verification for protocols like AXI or AHB Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB Excellent Team Player Experience in SOC Verification Experience in Formal verification Experience in verification of automotive protocols If interested please share your profile to:  sweta.srivastava@truechip.net Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp  
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Field-Programmable Gate Arrays Engineer at Centum T&S

  Hello Dear Readers, Currently, at Centum T&S vacancy for a Field-Programmable Gate Arrays Engineer role. About the job: Centum T&S is a Business unit of Centum Electronics Group offers a wide range of electronic and embedded systems design engineering services to Global Customers to help them realize complex products and sub systems. Centum T&S is an Electronics Design Center of Excellence, designing for mission critical projects in Aerospace/Space, Transportation, Medical Electronics, Defense Electronics etc. It has other design centers in the France, USA, Canada & Germany. The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager. What You'll...
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VLSI Digital Design Engineer at InnoPhase, Inc.

   Hello Dear Readers, Currently, InnoPhase Bangalore has a vacancy for a VLSI Digital Design Engineer role. INNOPHASE  is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments.  Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications. As a VLSI Design Engineer, you will be collaborating with a team of design engineers to develop novel ORAN SoC products for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations.  You will also be contributing to functional block design and integration to meet detailed device performance requirements. This role is an excellent opportunity for someone that enjoys...
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Staff Engineer - IC Design at Silicon Labs

  Hello Dear Readers, Currently, at Silicon Labs   Hyderabad  vacancy for a  Staff Engineer - IC Design role. About Silicon Labs: We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.   Why this position matters: As a Design Engineer in the R&D Digital team at Silicon Labs, Hyderabad, you will play a key role in designing digital blocks, Wireless MAC protocol implementations and Validation on FPGA.  You are responsible for the research and development of digital architectures and IPs fr...
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RTL Lead Design Engineer at Cadence Design System

  Hello Dear Readers, Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role. Position Description: RTL Design Engineer for DDR Memory Controller IP development team. Position is based in Bangalore. The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4. The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines. Position Requirements: BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. RTL Design using Verilog is a must. System Verilog experience and experience with UVM-based environment u...
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RTL Design Engineer at OpenFive

  Hello Dear Readers, Currently, at OpenFive vacancy for RTL Design Engineer role. OpenFive is looking for an individual with strong RTL Design skills. The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee, you will have the opportunity to work on any of the IPs in our portfolio, which are as follows:   100G/400G Ethernet Memory Controllers and Soft PHYs High Throughput/Low Latency Interlaken Controllers D2D Controllers We are a team with soft boundaries across teams and it is possible for you to work on one or more of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the entire tapeout process and post-silicon validation as well. Our Team focuses on high-quality of work and strong work ethic! We have...
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Finite State Machine (FSM) Modelling Using Verilog HDL

Hello Dear Readers, Today, I will explain how Finite State Machine (FSM) is modeling using Verilog HDL. The finite state machine (FSM) is a very important design block in the ASIC design. Most of the ASIC designs and controller design needs efficient and synthesizable state machines and are commonly called FSM. The FSMs can be described very efficiently by using the Verilog HDL and for ASIC design engineers. Basically, FSMs are predefined sequences on the preordered or defined events and are source synchronous designs. FSMs can be coded efficiently for the synthesizable outcome using the multiple- or single-procedural block. In the practical scenario, it is recommended to use the multiple-procedural blocks to describe the state machines. One of the procedural blocks can describe the combinational logic and level-sensitive to the inputs or the states. Whereas, the other procedural block can be edge sensitive to the positive edge of the clock or to the negative edge of the clock. 1)....
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