Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers, Today in this post I will provide some deep insight into what is happening in the semiconductor industry. So I hope you like it and enjoy it to improve your knowledge and awareness about the industry. So let's start it today we are discussing, The Importance of 3D IC Ecosystem Collaboration in the VLSI Market. As design teams continue to develop new generations of transformative products, the demand for computing remains relentless. Modern workloads have brought packaging technologies to the forefront for innovation and pushed the boundaries for silicon product design in terms of product performance, function and cost. Not too long ago, packaging technologies were thought of as inconvenient back-end processes. But times have changed, and rising advancements in artificial intelligence, big data, cloud computing, and autonomous vehicles have pushed the computing envelope unlike ever before (along with the need for packaging technologi...