Hello Dear Readers, Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
Hello Dear Readers, Currently, at Exiger Technologies Bangalore vacancy for the VLSI ASIC library design Engineer Trainee role. Job description: We are looking for B Tech/M Tech EC/EE graduates from the year 2022 batch to be trained as Std cell/Memory design/AMS verification and characterization engineers. The selected candidates will undergo intense training in the above areas and will have opportunities to work in Advanced Technology Nodes. Please note that we are not considering 2023 graduates for these roles. Requirements: Should have consistently scored above 70% in the academic programs Candidates should have preferably done projects or trained in the VLSI domain such as Analog Design/Digital Design/Physical design Good in CMOS-based design, circuit analysis Apply Here Connect with me 1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp