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Showing posts from February, 2023

Intern - Design & Technology Enablement at Global Foundries

Hello Dear Readers, Currently at Global Foundries vacancy for an Intern - Design & Technology Enablement role. GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. Introduction: As part of the PDK infrastructure group, the candidate will contribute to the software development of Process Design Kits and Design Manual infrastructure efficiency and innovation projects. Your Job : Contribute to the development and testing of PDK infrastructure group Propose and develop software-based solutions for technical needs Communicate with the team to understand the requirements and report status Other Responsibilities: Perform all activities

RTL Front End Design Engineers at Wafer Space Bangalore

Hello Dear Readers, Currently, at Wafer Space Bangalore vacancy for an RTL Front End Design Engineers role. Job Responsibilities: Chip integration of high complexity SOCs. Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action Formal Verification between RTL to Netlist and Netlist to Netlist Manual and Conformal ECO Running Lint (Spyglass) at SoC level. Chip-level integration and connectivity. Debugging FV failures ECO implementation. Desired Skills and Experience: 2 - 10 years of experience Sound knowledge in Micro Architecture design and RTL implementation Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs, and mobile SOCs is desirable Experience in Synthesis and pre-layout timing analysis Understanding of DFT flow is desirable Experiencing using clear case a must Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass

Intern at Marvell India

Hello Dear Readers, Currently, at Marvell India Bangalore vacancy for Intern role. About Marvell: At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better. The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below. The Opportunity: The intern would be working on an a

Silicon Validation Engineer at Texas Instruments

Hello Dear Readers, Currently, at Texas Instruments Bangalore vacancy for a Silicon Validation Engineer role. The requirement is for the precision DAC team to develop state-of-the-art precision digital to analog converters for catalog markets such as communication, test and measurement, automotive applications, and some very focused end equipment. Desired Experience: 1 to 3 years RESPONSIBILITIES: Understand device datasheet and arrive at a char plan Develop validation boards for device characterization Design char SW and validate the device for all use cases Run rigorous tests to find the breaking point of the device Present the Silicon Evaluation Data MUST HAVE: Understanding of analog circuits and electrical networks. Board-level design with analog components like DACs, ADCs, and OPAMPs. GOOD TO HAVE: Hands-on experience and hardware debug skills Knowledge of PCB design tools like Altium/Cadence Layout understanding for the high-precision signal chain Python Good oral and written co

AMS Engineer at Analog Devices

Hello Dear Readers, Currently, at Analog Devices Bangalore vacancy for AMS Engineer role. Analog Devices designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect. Analog, Mixed-Signal Verification Engineer focus on verification of high performance data converters. Job responsibilities: Learn AMS verification methodology and CAD tools Development of analog/behavioral models Validation of models to cross-check with the actual design behavior Create and own test verification as per the test plan to ensure high quality of design block Work closely with design team for complex debugs to resolve verification failures Run regressions and manage regression failures Skills Required: Basic understanding of VLSI circuits. Good knowledge of Verilog RTL coding including state machines, adders, multipliers, combinatori

Power Analysis in the VLSI Chip Design

Hello Dear Readers, Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments: Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to evaluate the die attach ma

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