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Showing posts from October, 2022

YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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What is Simulation? How Simulation Can Guide Real Engineering Design Decisions

  Hello Dear Readers,   Today in this post I will provide some deep insight into the simulation. So let's start. Simulation: Before software tools were developed, the verification of a particular circuit design could only be achieved by the construction of a prototype circuit. While the designer could use standard digital and analog techniques to design the circuit on paper. it was almost impossible to determine whether the circuit would perform as expected in practice. These 'bread boarded' prototype circuits were constructed using discrete components such as individual logic gates, transistors, resistors, capacitors, etc. When built, the circuit would be thoroughly tested and design modifications made on the basis of these tests. The next version of the prototype was then constructed and the process repeated. Such an approach technique was very time-consuming and expensive and resulted in a very long development time. Translation from breadboard to chip often resulted in ...
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CPU Verification Engineer at NVIDIA Bangalore

  Hello Dear Readers, Currently at Nvidia Bangalore vacancy for a CPU Verification Engineer role. What you’ll be doing: Work on NVIDIA's next generation CPU. Verify micro-architecture/architecture features at unit level or subsystem or full chip testbenches including FPGA/Silicon. Work along with CPU architects in creating verifiable designs. What we need to see: Experience with full stack development - from verifying sequences at SW simulator level, to getting the overall end-to-end sequence working on silicon with a full SW stack. Strong verification fundamentals and able to juggle working on full chip testbenches and on FPGA/Silicon. Proficient in CPU architecture (ARM knowledge is desirable), Verilog, SystemVerilog and possess strong debugging skills. Bachelors/Masters or equivalent experience in Computer Science or electrical engineering from a reputed engineering college and 3+ years of industry experience. Ways to stand out from the crowd: Experience on CPU unit/microarchit...
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Staff Engineer - IC Design at Silicon Labs

  Hello Dear Readers, Currently, at Silicon Labs   Hyderabad  vacancy for a  Staff Engineer - IC Design role. About Silicon Labs: We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.   Why this position matters: As a Design Engineer in the R&D Digital team at Silicon Labs, Hyderabad, you will play a key role in designing digital blocks, Wireless MAC protocol implementations and Validation on FPGA.  You are responsible for the research and development of digital architectures and IPs fr...
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Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
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ASIC Design Engineer at Juniper Networks

Hello Dear Readers, Currently, at Juniper Networks Banglore vacancy for an ASIC Design Engineer role. Job Description: “This position has the potential to be transferred to Juniper USA after completing one year of employment.  The transfer will be subject to standard transfer eligibility requirements.” Juniper Development and Innovation (JDI) Silicon Development group is responsible for creating the custom chips that are at the heart of most of Juniper's products. JDI Silicon Team seeks ASIC Engineers to develop next generation of ASICs for new core routers, switches, and firewalls. Our Silicon team delivers on-time and error-free, high-performing, scalable, lowest cost, power efficient Silicon that is widely deployable and beats the competition. ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature-rich without sacrificing in performance.  We have developed 3 generations of high-end router chipsets.   JUNIP...
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Design Engineer II at Cadence Design System

  Hello Dear Readers, Currently, at Cadence Banglore vacancy for the Design Engineer II role. Job Description: 0-2+ years of design verification experience. B.Tech/B.E/M.Tech/M.E in Electronics/Electrical/Computer Science Thorough understanding of UVM/SV based verification environment to build flexible and reusable complex testbenches Working experience on advanced protocols like PCIe/USB/Ethernet Proven experience in leading a verification project to completion. Experience in Emulation and Formal Verification will be plus Exposure to scripting languages (Perl/Shell/Python) Self-starter and learner with a passion for getting the job done on time with great quality Strong problem solving and analytical skills Excellent verbal and written communications skills Apply Here Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp
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RTL Lead Design Engineer at Cadence Design System

  Hello Dear Readers, Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role. Position Description: RTL Design Engineer for DDR Memory Controller IP development team. Position is based in Bangalore. The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4. The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines. Position Requirements: BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. RTL Design using Verilog is a must. System Verilog experience and experience with UVM-based environment u...
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