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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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RTL Lead Design Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role.

Position Description:


  • RTL Design Engineer for DDR Memory Controller IP development team.
  • Position is based in Bangalore.
  • The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence.
  • All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
  • The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

  • BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM-based environment usage / debugging are required.
  • AXI3/4 experience is a desired.
  • DDR Memory controller and protocol experience are highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage. 

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