Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers,
Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role.
Position Description:
- RTL Design Engineer for DDR Memory Controller IP development team.
- Position is based in Bangalore.
- The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence.
- All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
- The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
Position Requirements:
- BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
- RTL Design using Verilog is a must.
- System Verilog experience and experience with UVM-based environment usage / debugging are required.
- AXI3/4 experience is a desired.
- DDR Memory controller and protocol experience are highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
- Prior experience in IP development teams would be an added advantage.
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