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SRAM/Memory CAD Engineer at Qualcomm

  Hello Dear Readers, Qualcomm Bangalore currently has a vacancy for an SRAM/Memory CAD Engineer. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems,  Digital/Analog/RF/optical  systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronic...
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RTL Lead Design Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role.

Position Description:


  • RTL Design Engineer for DDR Memory Controller IP development team.
  • Position is based in Bangalore.
  • The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence.
  • All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
  • The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

  • BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM-based environment usage / debugging are required.
  • AXI3/4 experience is a desired.
  • DDR Memory controller and protocol experience are highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage. 

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