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ASIC Physical Design Engineer at HPE

  Hello Dear Readers, At HPE Bangalore, there is a vacancy for a Physical Design Engineer role. This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Aruba  is an HPE Company, and a leading ...
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RTL Lead Design Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role.

Position Description:


  • RTL Design Engineer for DDR Memory Controller IP development team.
  • Position is based in Bangalore.
  • The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence.
  • All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
  • The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

  • BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM-based environment usage / debugging are required.
  • AXI3/4 experience is a desired.
  • DDR Memory controller and protocol experience are highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage. 

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