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Senior Eng CAD Engineering at Global Foundries

Hello Dear Readers,   Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...
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RTL Lead Design Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Banglore vacancy for the RTL Lead Design Engineer role.

Position Description:


  • RTL Design Engineer for DDR Memory Controller IP development team.
  • Position is based in Bangalore.
  • The role would include design and support of the RTL of the DDR Memory Controller solution of Cadence.
  • All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
  • The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

  • BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM-based environment usage / debugging are required.
  • AXI3/4 experience is a desired.
  • DDR Memory controller and protocol experience are highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage. 

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