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Showing posts from January, 2021

Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Multiplexer Verilog Code

Hello Dear Readers, Here I have giving Verilog code of 32-bit Multiplexer which is a common digital system block.  A multiplexer selects an input from multiple inputs. The following code implements a 32-bit 2-to-1 multiplexer as well as a 4-to-1 multiplexer using a function . The [31:0] denotes a bus that has 32 bits.  So Let's Start it code. Verilog Code: 1) Multiplexer Using Dataflow Level: module mux2to1 (a0,a1,s,y); // multiplexer, 32 bits   // inputs, 32 bits input [31:0] a0, a1;       // input selection line, 1 bit       input s;      // output, 32 bits          output [31:0] y;        // ternary operator is used so if (s==1) y=a1; else y=a0;      assign y = s ? a1 : a0;       endmodule Now there is also a function facility available in Verilog similar to C language such functions are sections of Verilog code that allow the Digital Designer to write more reusable and maintainable code. Often a function is created when the same operation is done over and over throughout Verilo
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CMOS Logic Gates Using Verilog HDL

  CMOS Logic Gate Design  Hello Dear Readers, This section describes how to used a low-level CMOS transistor to design basic digital logic gates and its implementation in Verilog HDL. In CMOS technology, both PMOS as well as NMOS transistors, are used. PMOS is active when the input signal will be 0(Low) level, and NMOS is active when the input signal will be 1(High) level. In below figures show the basic design of the CMOS inverter, NAND, NOR gates. We know if we made AND or OR gate from NAND or NOR respectively, then we need two more transistors of the inverter. That's why we see in the gate array chips contain an array of the universal gates only. In the below section, I have written the whole Verilog code of all the gates with testbench code. Verilog Code: module CMOS_Gates(input a,b,output f,f1,f2     ); supply1 vdd; supply0 gnd; wire w1,w2; //NOT gate // pmos (drain, source, gate); pmos t1 (f, vdd, a); // nmos (drain, source, gate); nmos t2 (f, gnd, a); //NAND gate // pmos (dr
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Difference between CISC and RISC In Computer System

 CISC Vs. RISC Hello Dear Reader, Most Welcome in my second blog I have started this one after I got succeded in my first blog  https://nishitnathwani.blogspot.com/   Today I will be discussing the difference between CISC and RISC two types of hardware systems inside the computer system. CISC is the general name for CPUs that have a complex instruction set. An instruction set is said to be complex if there are some instructions that perform complex operations or the instruction formats are not uniform. The Intel x86 family, Motorola 68000 series, PDP-11, and VAX are examples of CISC. The CISC instruction set tries to enhance the code density so that a computer system can use a small amount of memory, including cache, to store as many instructions as possible for reducing the cost and improving performance. CISC adopts two measures to reduce the code size – it lets an instruction perform as many operations as possible and makes the encoding of each instruction as short as possible. The
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