Hello Dear Readers, Currently, at Analog Devices Bangalore vacancy for AMS Engineer role. Analog Devices designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect. Analog, Mixed-Signal Verification Engineer focus on verification of high performance data converters. Job responsibilities: Learn AMS verification methodology and CAD tools Development of analog/behavioral models Validation of models to cross-check with the actual design behavior Create and own test verification as per the test plan to ensure high quality of design block Work closely with design team for complex debugs to resolve verification failures Run regressions and manage regression failures Skills Required: Basic understanding of VLSI circuits. Good knowledge of Verilog RTL coding including state machines, adders, multiplier...

Hello Dear Readers,   Today, I will explain how binary, gray, one-hot encoding FSM design using Verilog HDL. 1). Binary Encoding: Binary encoding style can be used if the area requirement is a constraint on the design. In this encoding style state parameters for the binary encoding are represented in the binary format. Two-Bit Binary Up-Counter FSM: Two-bit binary counter FSM is described below, the number of states is equal to 4 and it needs four state variables ‘s0,’ ‘s1,’ ‘s2,’ and ‘s3.’ The number of flip-flops used to represent the functionality of the counter is equal to 2. The state transition table and the state transition diagram is shown in Fig.1 and Fig.2. The transition from one state to another state occurs on the positive edge of the clock. The default state is ‘s0’ and it is the reset state. So outcome is Moore machine as the output is a function of the current state only. Fig.1 State Transition Table Fig.2 State Diagram Verilog Code: module binary_cou...