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Showing posts from January, 2024

VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Semiconductor Engineer at Micron Technology

Hello Dear Readers, Currently, at Micron Technology vacancy for a Semiconductor Engineer role. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About profile: As a Semiconductor Engineer, you will work in a highly innovative, motivated, young and dynamic team involved in the design and verification of state of the art memory (DRAM/NAND) component and system solutions. You will need to have the ability to Design, verify functionality and provide solutions to help the timely delivery of these designs. You will also need to have the ability to come up with EDA flows & automation to help design teams, design best in class memory components and validate them at module/system level. Preferred Skills: Strong understanding of Computer Architecture, Circuits & Signals, and skilled in C, C++, Python. Strong fun...
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VLSI &Embedded Systems Design Engineer at Garudaven Private Limited

Hello Dear Readers, Currently, at Garudaven Private Limited vacancy for a VLSI &Embedded Systems Design Engineer role. Garudaven is a technology-driven company that offers tailored IT solutions to meet the unique needs of each client. Our suite of services encompasses everything from digital transformation and cloud services to cybersecurity and IT consulting. Our goal is twofold: To stay ahead of the curve in a constantly evolving tech landscape and to empower our clients with state-of-the-art IT solutions. We work with startups, established enterprises and organizations that are looking for a partner in success. We are located in Bengaluru, India. Role Description: This is a full-time on-site role located in Bengaluru for a VLSI & Embedded Systems Engineer. The engineer will specialize in designing complex circuits and embedded systems that meet performance, power, area, and reliability objectives, as well as developing advanced techniques for debugging and bringing up n...
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Associate Digital Design Engineer at Analog Devices

Hello Dear Readers, Currently, at Analog Devices vacancy for an Associate Digital Design Engineer role. Analog Devices, Inc.  is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art. Digital IC Design at ADI: ADI has long been considered the industry leader in high performance analog/mixed signal semiconductors, and we specialize in bridging the real word to the digital world: what is increasingly referred to ...
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Std cell Circuit Design & Characterization Engineer at Cognitive Design Technology Pvt Ltd

Hello Dear Readers, Currently, at Cognitive Design Technology Pvt Ltd vacancy for a Std cell Circuit Design & Characterization role. Specific Responsibilities: Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.). Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond). Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products. Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team. Maintain a relationship and collaborate with 3 rd party C...
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SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...
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SDC(Synopsys Design Constraints) contents part 3

  Dear readers, today we will be discussing the IO-related constraints mentioned in the SDC file. The reason for defining the commands in the SDC file and their significance. STA cannot check the paths which are not constrained. Therefore, all paths must be constrained. 5. set_input_delay      This tells us how much time data will be delayed with respect to the clock to reach the input port of our design. That is the delay used by the external logic. So, the designer can estimate how much time is left for internal logic to meet the targets. For example, The delay at the input port defined by the combined delay of clock to Q delay of UFF0 and combinational delay. This delay is defined with respect to the CLKA. This is specified as          set_input_delay 1.5 -clock CLKA  [get_ports INP] Input delay can be specified for worst case slow (max) corner and best case fast (min) corner.              ...
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