Skip to main content

Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...

VLSI &Embedded Systems Design Engineer at Garudaven Private Limited

Hello Dear Readers,

Currently, at Garudaven Private Limited vacancy for a VLSI &Embedded Systems Design Engineer role.

Garudaven is a technology-driven company that offers tailored IT solutions to meet the unique needs of each client. Our suite of services encompasses everything from digital transformation and cloud services to cybersecurity and IT consulting. Our goal is twofold: To stay ahead of the curve in a constantly evolving tech landscape and to empower our clients with state-of-the-art IT solutions. We work with startups, established enterprises and organizations that are looking for a partner in success. We are located in Bengaluru, India.

Role Description:

This is a full-time on-site role located in Bengaluru for a VLSI & Embedded Systems Engineer. The engineer will specialize in designing complex circuits and embedded systems that meet performance, power, area, and reliability objectives, as well as developing advanced techniques for debugging and bringing up new silicon. The successful candidate will collaborate with cross-functional teams, manage complex designs, and report to project managers, attending regular design reviews and interacting with different teams to ensure that the product meets specifications.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Demonstrable experience in working with ASIC/FPGA design/validation/verification, schematic design, simulation, hardware/software debugging, and design documentation
  • Excellent knowledge of digital signal processing, micro-architecture design, and system-on-chip (SoC) design flows, including RTL design in Verilog/VHDL, synthesis, place and route, and static timing analysis (STA)
  • Proficiency in programming languages such as C/C++, scripting languages such as TCL/Perl, and industry-standard CAD tools such as Synopsys, Cadence, and Mentor Graphics
  • Strong problem-solving skills, analytical thinking, and attention to detail
  • Ability to work independently and as part of a team, and manage multiple priorities in a fast-paced environment
  • Excellent verbal and written communication skills in English
  • Experience with SoC design in the areas of multimedia, image processing, or machine learning is a plus

   


Apply Here

Comments

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...