Skip to main content

Power Architecture Engineer at Nvidia

Hello Dear Readers,   Currently at Nvidia vacancy for Power Architecture Engineer role. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you’ll be doing: Be part of NVIDIA Power Architecture Group that owns end-to-end power aspects such ...
Post a Comment

VLSI &Embedded Systems Design Engineer at Garudaven Private Limited

Hello Dear Readers,

Currently, at Garudaven Private Limited vacancy for a VLSI &Embedded Systems Design Engineer role.

Garudaven is a technology-driven company that offers tailored IT solutions to meet the unique needs of each client. Our suite of services encompasses everything from digital transformation and cloud services to cybersecurity and IT consulting. Our goal is twofold: To stay ahead of the curve in a constantly evolving tech landscape and to empower our clients with state-of-the-art IT solutions. We work with startups, established enterprises and organizations that are looking for a partner in success. We are located in Bengaluru, India.

Role Description:
This is a full-time on-site role located in Bengaluru for a VLSI & Embedded Systems Engineer. The engineer will specialize in designing complex circuits and embedded systems that meet performance, power, area, and reliability objectives, as well as developing advanced techniques for debugging and bringing up new silicon. The successful candidate will collaborate with cross-functional teams, manage complex designs, and report to project managers, attending regular design reviews and interacting with different teams to ensure that the product meets specifications.

Qualifications:
  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Demonstrable experience in working with ASIC/FPGA design/validation/verification, schematic design, simulation, hardware/software debugging, and design documentation
  • Excellent knowledge of digital signal processing, micro-architecture design, and system-on-chip (SoC) design flows, including RTL design in Verilog/VHDL, synthesis, place and route, and static timing analysis (STA)
  • Proficiency in programming languages such as C/C++, scripting languages such as TCL/Perl, and industry-standard CAD tools such as Synopsys, Cadence, and Mentor Graphics
  • Strong problem-solving skills, analytical thinking, and attention to detail
  • Ability to work independently and as part of a team, and manage multiple priorities in a fast-paced environment
  • Excellent verbal and written communication skills in English
  • Experience with SoC design in the areas of multimedia, image processing, or machine learning is a plus

   


Apply Here

Comments

Post a Comment

Popular posts from this blog

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to ev...
5 comments
Read more