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Showing posts with the label ARM Assembly

VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Field-Programmable Gate Arrays Engineer at Centum T&S

  Hello Dear Readers, Currently, at Centum T&S vacancy for a Field-Programmable Gate Arrays Engineer role. About the job: Centum T&S is a Business unit of Centum Electronics Group offers a wide range of electronic and embedded systems design engineering services to Global Customers to help them realize complex products and sub systems. Centum T&S is an Electronics Design Center of Excellence, designing for mission critical projects in Aerospace/Space, Transportation, Medical Electronics, Defense Electronics etc. It has other design centers in the France, USA, Canada & Germany. The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager. What You'll...
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SYSTEM VIP Verification Engineer at Cadence Design System

  Hello Dear Readers, Currently, at Cadence Design System vacancy for a SYSTEM VIP Verification Engineer role. Job Description:  Good experience on SOC level performance analysis and System level scenarios validation Hands-on DDR interface, peripherals Ethernet, DMA transfer and System level I/O coherency testing Worked on the AXI/Ace/Other Amba protocols debug and C test case development Overall hands on exp on SOC DV flows and test case development for ARM based SOCs Advantage: Good knowledge in software languages (C++/PYTHON/JAVA/JAVA Script) Customer support experience Knowledge in scripting Perl /shell scripting or similar languages ·         Educational Qualification :  BE/BTech or ME/ M.Tech  Graduate wit.h Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses. If interested please share your profile to:  rajesha@cadence.com ...
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Silicon CPU/ SOC Verification Engineer at Rivos Inc

    Hello Dear Readers, Currently at Rivos Bangalore vacancy for a Silicon CPU/ SOC Verification Engineer role. Positions are open for full-time and Co-op/internship in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal. We are looking for all levels of talent, from entrance to advanced level of experience. Responsibilities: Work closely with architecture and RTL designers on verifying the functionality correctness of the design Reviewing Architecture and Design Specifications Develop test plans and test environments Develop tests in assembly, C/C++, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers in SystemVerilog or C-base transactors to verify the design Write assertions and apply formal verification to the designImplementing test benches, generating...
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CPU Logic Design Engineer at NVIDIA Bangalore

  Hello Dear Readers, Currently at Nvidia Bangalore vacancy for a CPU Logic Design Engineer. What you'll be doing: As a member of our CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip. Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation. Collaborate with our verification team to verify the correctness of your unit. Work with implementation to achieve your timing, area, performance and power goals. Assist with timing closure of super units. What we need to see: A Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience. 2+ years of experience in processor or other related high-performance semiconductor designs. Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, br...
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ARM Assembly Language Practice Question And Answer Part-4

  Hello Dear Readers,   Today in this post I will provide some basics to advanced ARM's assembly language practice QA part-4, I have used the Keil tool for code writing. Q-1).  Write an assembly language program that performs a mode change by modifying the contents of the CPSR.    a. The mode you should change to is user mode, and you have to modify the mode field of CPSR by the value of 0x10.    b. This assumes that the current mode is a privileged mode such as supervisor mode. Code: ; program which changes the microprocessor mode  masking equ 0x1f  user_mode equ 0x10   area change, code, readonly entry   MRS R0,CPSR; read the status of the microprocessor   BIC R0, R0,#masking; apply the masking bit   ORR R0,R0,#user_mode ; set the mode user_mode   MSR CPSR_C,R0 ; written back with control_field_mask   END  Output: Q-2).  Write an assembly language program that generates S...
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