Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers, Today in this series of posts, I will provide some deep insight into the RISC-V microprocessor and its Implementation using Verilog HDL. RISC-V is an open-source instruction set architecture (ISA) designed for modern computer processors. It is a relatively new ISA that has gained popularity recently due to its flexibility, simplicity, and open-source nature. The name "RISC-V" stands for Reduced Instruction Set Computing - Five, which refers to the fact that it is based on a simple, streamlined set of instructions. One of the key features of RISC-V is its modular design, which allows for customization and scalability. This means that designers can choose which instructions to include and how to implement them, which can result in more efficient and specialized processors. Additionally, because RISC-V is open-source, it is free to use and can be modified by anyone, making it a popular choice for academic research and experimentation. RISC-V also incl...