Hello Dear Readers, Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
Hello Dear Readers, Today in this series of posts, I will provide some deep insight into the RISC-V microprocessor and its Implementation using Verilog HDL. RISC-V is an open-source instruction set architecture (ISA) designed for modern computer processors. It is a relatively new ISA that has gained popularity recently due to its flexibility, simplicity, and open-source nature. The name "RISC-V" stands for Reduced Instruction Set Computing - Five, which refers to the fact that it is based on a simple, streamlined set of instructions. One of the key features of RISC-V is its modular design, which allows for customization and scalability. This means that designers can choose which instructions to include and how to implement them, which can result in more efficient and specialized processors. Additionally, because RISC-V is open-source, it is free to use and can be modified by anyone, making it a popular choice for academic research and experimentation. RISC-V also incl...