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Showing posts with the label My Designed Project

RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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What is RISC-V Microprocessor and Implementation using Verilog HDL Part-1

  Hello Dear Readers,   Today in this series of posts, I will provide some deep insight into the RISC-V microprocessor and its Implementation using Verilog HDL. RISC-V is an open-source instruction set architecture (ISA) designed for modern computer processors. It is a relatively new ISA that has gained popularity recently due to its flexibility, simplicity, and open-source nature. The name "RISC-V" stands for Reduced Instruction Set Computing - Five, which refers to the fact that it is based on a simple, streamlined set of instructions. One of the key features of RISC-V is its modular design, which allows for customization and scalability. This means that designers can choose which instructions to include and how to implement them, which can result in more efficient and specialized processors. Additionally, because RISC-V is open-source, it is free to use and can be modified by anyone, making it a popular choice for academic research and experimentation. RISC-V also incl...
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

   Hello Dear Readers,   Today in this post I will discuss further the  FIR Filter Front-End  implementation at the back-end side by performing the RTL to GDS-II tool Q-flow. For the Installation of the tool follow the steps which are mentioned here below, I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point. Fig. 1 Q-flow Physical Design Flow Fig. 2 Final Layout of FIR filter Connect with me  1.Linkedln 2.Instagram 3.Facebook
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Carry Lookahead Adder Design And Implementation of Generic Parametrized Adder Using Verilog HDL

  Hello Dear Readers, Today In this post I have designed a carry-lookahead adder design and implemented its parametrized version using Verilog HDL and analysis that design for the desire output. First of all, I have designed CLA based on the theory described in the below video of the Neso Academy.       Verilog Code: module add (a, b, c, g, p, s); // adder and g, p input a, b, c; // inputs: a, b, c; output g, p, s; // outputs: g, p, s; assign s=a ^ b ^ c; // output: sum of inputs assign g = a & b; // output: carry generator assign p = a | b; // output: carry propagator endmodule module gp (g,p,c_in,g_out,p_out,c_out); // carry generator, carry propagator input [1:0] g, p; // lower level 2-set of g, p input c_in; // lower level carry_in output g_out,p_out,c_out; // higher level g, p, carry_out assign g_out = g[1] | p[1] & g[0]; // higher level carry generator assign p_out = p[1] & p[0]; // higher level carry propagator assign c_out = g[0] | p[0] & c_in...
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Designing of the 4 Tap FIR Filter Using Verilog HDL

  Hello Dear Readers, Here I have designed a 4 tap FIR filter using Verilog languages and some parts of the Python language to just print the input and output samples that are generating Verilog HDL. So Let's see the Code of the complete system. So first of all FIR filter is a system which transfer function has a finite number of impulsive points corresponding to the type of the filters such as high pass, low pass, bandpass, etc... so it has generally two types of structure as shown in the below, FIR Filter Structures: Here I have used the first structure in which first multiply input samples with impulse responses so without delay products is available now we give delays to that data means here we have implemented shifted adder for MAC operation of the digital filter. Verilog Code: module fir_4tap(input Clk,input signed [7:0] Xin,output reg signed [15:0] Yout);     //Internal variables. wire signed   [7:0] H0,H1,H2,H3; wire signed   [15:0] MCM_bl...
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Design of the 3 Stage Pipeline Microprocessor Using Verilog

  Hello Dear Readers, First of all thanks for giving motivation on my first of designing microprocessor.  DESIGN OF THE SINGLE CYCLE MICROPROCESSOR USING VERILOG HDL . So now in this post, i will explain the 3 stages of the pipeline microprocessors namely the Fetch Unit , Decode Unit , and Execute Unit . So Let's start designing based on the specification given below. Stage-1: Fetch Unit Fetch Unit comprises half-word addressable instruction memory. It takes PC as input and gives the instruction as an output. PC is also incremented by PC=PC+1. Stage-2: Decode Unit Decode Unit reads the fetched instruction and decodes the address of two source operands and destination register. Also, it generates the immediate data. Register Bank reads the value of source operands (Rs1 and Rs2) at negative level of the clock, and writes the data in the destination register (Rd) at positive level of clock. Control Unit uses 4-bit opcode bits to determine the type of instruction.  Stage-3: E...
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