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Senior Eng CAD Engineering at Global Foundries

Hello Dear Readers,   Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

  Hello Dear Readers, 

Today in this post I will discuss further the FIR Filter Front-End implementation at the back-end side by performing the RTL to GDS-II tool Q-flow.

For the Installation of the tool follow the steps which are mentioned here below,





I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point.

Fig. 1 Q-flow Physical Design Flow

Fig. 2 Final Layout of FIR filter


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Comments

  1. Anonymous30 December 2021 at 05:19

    Completed sir FIR filter complete path I don't have words for you but keep it up and so much thank you sir and love you.

    ReplyDelete
  2. Anonymous1 January 2022 at 04:53

    Your website is my favourite one for project understanding.

    ReplyDelete
  3. Anonymous8 January 2022 at 19:00

    Superb post and project idea hope to see more advanced topics in future.

    ReplyDelete
  4. Anonymous18 January 2022 at 20:40

    Good post keep it up and do some advanced levels such as System Verilog, UVM etc...

    ReplyDelete

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