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Regular Pattern Search Using grep, awk and sed

Hello, Dear Readers,   In this post, I will share some deep insights into regular pattern searching using grep, awk, and sed. In VLSI/EDA flows, engineers frequently work with large Innovus, Voltus, STA, EMIR, synthesis and simulation reports. Linux commands such as grep , awk , and sed provide a fast way to search, filter and process this data without opening huge files manually. 1. Regular Expressions: A regular expression (regex) defines a pattern for searching text. Common patterns: Pattern Meaning Example . Any character V.D * Zero or more ab* + One or more ab+ [0-9] Digit U [0-9] [a-z] Lowercase [a-z] + ^ Start of line ^VDD $ End of line VDD$ ` ` OR `VDD VSS` For example: grep -E 'ERROR|WARNING|FATAL' voltus.log Searches for any of the three patterns. 2. grep — Search and Filter: grep is mainly used to find matching lines . Basic search grep 'VIOLATION' report.rpt Case-insensitive search grep -i 'error' run.log Show line numbers grep -n 'VIOLATION...
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

  Hello Dear Readers, 

Today in this post I will discuss further the FIR Filter Front-End implementation at the back-end side by performing the RTL to GDS-II tool Q-flow.

For the Installation of the tool follow the steps which are mentioned here below,





I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point.

Fig. 1 Q-flow Physical Design Flow

Fig. 2 Final Layout of FIR filter


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  1. Anonymous30 December 2021 at 05:19

    Completed sir FIR filter complete path I don't have words for you but keep it up and so much thank you sir and love you.

    ReplyDelete
  2. Anonymous1 January 2022 at 04:53

    Your website is my favourite one for project understanding.

    ReplyDelete
  3. Anonymous8 January 2022 at 19:00

    Superb post and project idea hope to see more advanced topics in future.

    ReplyDelete
  4. Anonymous18 January 2022 at 20:40

    Good post keep it up and do some advanced levels such as System Verilog, UVM etc...

    ReplyDelete

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