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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

  Hello Dear Readers, 

Today in this post I will discuss further the FIR Filter Front-End implementation at the back-end side by performing the RTL to GDS-II tool Q-flow.

For the Installation of the tool follow the steps which are mentioned here below,





I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point.

Fig. 1 Q-flow Physical Design Flow

Fig. 2 Final Layout of FIR filter


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Comments

  1. Anonymous30 December 2021 at 05:19

    Completed sir FIR filter complete path I don't have words for you but keep it up and so much thank you sir and love you.

    ReplyDelete
  2. Anonymous1 January 2022 at 04:53

    Your website is my favourite one for project understanding.

    ReplyDelete
  3. Anonymous8 January 2022 at 19:00

    Superb post and project idea hope to see more advanced topics in future.

    ReplyDelete
  4. Anonymous18 January 2022 at 20:40

    Good post keep it up and do some advanced levels such as System Verilog, UVM etc...

    ReplyDelete

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