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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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RTL to GDS-II of FIR Filter Using Open Source Tool Q-flow

  Hello Dear Readers, 

Today in this post I will discuss further the FIR Filter Front-End implementation at the back-end side by performing the RTL to GDS-II tool Q-flow.

For the Installation of the tool follow the steps which are mentioned here below,





I have tested my FIR filter Verilog code using Q-flow as shown in Fig. 1 successfully. In which I have selected OSU018 which is 180nm Technology Node. After completing all the steps last one is to click on Edit Layout options will go to us in the Magic tool for displaying the final layout of our RTL code as shown in FIg. 2 where we can see also zero DRC error at top of the middle point.

Fig. 1 Q-flow Physical Design Flow

Fig. 2 Final Layout of FIR filter


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  1. Anonymous30 December 2021 at 05:19

    Completed sir FIR filter complete path I don't have words for you but keep it up and so much thank you sir and love you.

    ReplyDelete
  2. Anonymous1 January 2022 at 04:53

    Your website is my favourite one for project understanding.

    ReplyDelete
  3. Anonymous8 January 2022 at 19:00

    Superb post and project idea hope to see more advanced topics in future.

    ReplyDelete
  4. Anonymous18 January 2022 at 20:40

    Good post keep it up and do some advanced levels such as System Verilog, UVM etc...

    ReplyDelete

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