Hello, Dear Readers, In this post, I will share some deep insights into regular pattern searching using grep, awk, and sed. In VLSI/EDA flows, engineers frequently work with large Innovus, Voltus, STA, EMIR, synthesis and simulation reports. Linux commands such as grep , awk , and sed provide a fast way to search, filter and process this data without opening huge files manually. 1. Regular Expressions: A regular expression (regex) defines a pattern for searching text. Common patterns: Pattern Meaning Example . Any character V.D * Zero or more ab* + One or more ab+ [0-9] Digit U [0-9] [a-z] Lowercase [a-z] + ^ Start of line ^VDD $ End of line VDD$ ` ` OR `VDD VSS` For example: grep -E 'ERROR|WARNING|FATAL' voltus.log Searches for any of the three patterns. 2. grep — Search and Filter: grep is mainly used to find matching lines . Basic search grep 'VIOLATION' report.rpt Case-insensitive search grep -i 'error' run.log Show line numbers grep -n 'VIOLATION...
Hello Dear Readers, Today in this post I will provide some techniques for timing optimization in ASIC Design. Timing Optimization Techniques are as follows: 1. Mapping: Mapping converts primitive logic cells found in a netlist to technology-specific logic gates found in the library on the timing critical paths. 2. Unmapping: Unmapping converts the technology-specific logic gates in the netlist to primitive logic gates on the timing critical paths. 3. Pin Swapping : Pin swapping optimization examines the slacks on the inputs of the gates on the worst timing paths and optimizes the timing by swapping nets attached to the input pins, so the net with the least amount of slack is put on the fastest path through the gate without changing the function of the logic. 4. Buffering: Buffers are inserted in the design to drive a load that is too large for a logic cell to efficiently drive. If the net is too long then the net is broken and buffers are inserted to improve the transition...