Hello Dear Readers, Currently, after succeeding up to this today, I will start new NPTEL courses per VLSI and ECE branch job profiles. So let's start with today's RTL/FPGA engineer profiles courses. 1. HARDWARE MODELING USING VERILOG: Coordinators: PROF. INDRANIL SENGUPTA  Department of Computer Science and Engineering IIT Kharagpur INTENDED AUDIENCE: CSE, ECE, EE  PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++  INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx COURSE OUTLINE: The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.  ABOUT INSTRUCTOR:   Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. H...