Static Timing Analysis Practice Questions

 Hello Dear Readers, 

Today I have designed this page for doing exercises regarding STA-related Questions.

Q-1:

The circuit in Fig. 1. is the internal layout of a custom-built chip. The tpd for each gate is listed below it. The delays for the register are all the same and listed in the lower right corner. What is the Maximum Clock Frequency of the below gate-level netlist?

Fig. 1

Solution:

Q-2:

For each of the following circuits: 

 (i). Calculate the worst-case pin-to-pin combinational delay, clock-to-output delay, and register-to-register delay. 

   (ii). Use this data to find the maximum clock frequency. 

  (iii). Calculate tsu and thd for the external inputs.

Fig. 2

Fig. 3

Q-3: Are Setup and Hold times of the flip-flop is intrinsic parameters or design parameters.

Q-4: Setup and Hold times of the flip-flop are controllable or not, explain your answer.

Here I will upload more as I will come across any good questions. Thanks for reading 

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