Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Hello Dear Readers,
Today I have designed this page for doing exercises regarding STA-related Questions.
Q-1:
The circuit in Fig. 1. is the internal layout of a custom-built chip. The tpd for each gate is listed below it. The delays for the register are all the same and listed in the lower right corner. What is the Maximum Clock Frequency of the below gate-level netlist?
Fig. 1 |
Q-2:
Here I will upload more as I will come across any good questions. Thanks for reading
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For each of the following circuits:
(i). Calculate the worst-case pin-to-pin combinational delay, clock-to-output delay, and register-to-register delay.
(ii). Use this data to find the maximum clock frequency.
(iii). Calculate tsu and thd for the external inputs.
Q-3: Are Setup and Hold times of the flip-flop is intrinsic parameters or design parameters.
Q-4: Setup and Hold times of the flip-flop are controllable or not, explain your answer.
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