Hello Dear Readers, Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...
Hello Dear Readers,
Today I have designed this page for doing exercises regarding STA-related Questions.
Q-1:
The circuit in Fig. 1. is the internal layout of a custom-built chip. The tpd for each gate is listed below it. The delays for the register are all the same and listed in the lower right corner. What is the Maximum Clock Frequency of the below gate-level netlist?
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| Fig. 1 |
Q-2:
Here I will upload more as I will come across any good questions. Thanks for reading
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For each of the following circuits:
(i). Calculate the worst-case pin-to-pin combinational delay, clock-to-output delay, and register-to-register delay.
(ii). Use this data to find the maximum clock frequency.
(iii). Calculate tsu and thd for the external inputs.
Q-3: Are Setup and Hold times of the flip-flop is intrinsic parameters or design parameters.
Q-4: Setup and Hold times of the flip-flop are controllable or not, explain your answer.






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