Skip to main content

YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
1 comment

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

 Hello Dear Readers,

Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review.

Book Name: Computer Principles and Design in Verilog  HDL


Description: 

Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills

  • Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design
  • Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation
  • Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques
  • A companion website includes color figures, Verilog HDL codes, extra test benches not found in the book, and PDFs of the figures and simulation waveforms for instructors

About The Author:

Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan.
Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost, and published it in IEEE ICCD'96 and ICCD'97.

Contents:

1. Computer Fundamentals and Performance Evaluation
2. A Brief Introduction to Logic Circuits and Verilog HDL
3. Computer Arithmetic Algorithms and Implementations 
4. Instruction Set Architecture and ALU Design  
5. Single-Cycle CPU Design in Verilog HDL 
6. Exceptions and Interrupts Handling and Design in Verilog HDL  
7. Multiple-Cycle CPU Design in Verilog HDL  
8. Design of Pipelined CPU with Precise Interrupt in Verilog HDL  
9. Floating-Point Algorithms and FPU Design in Verilog HDL
10. Design of Pipelined CPU with FPU in Verilog HDL 
11. Memory Hierarchy and Virtual Memory Management  
12. Design of Pipelined CPU with Caches and TLBs in Verilog HDL
13. Multithreading CPU and Multicore CPU Design in Verilog HDL  
14. Input/Output Interface Controller Design in Verilog HDL  
15. High-Performance Computers and Interconnection Networks  


Connect with me 

Labels:

Comments

  1. Anonymous30 December 2022 at 02:26

    One of the best book I found till thanks for your review.

    ReplyDelete
  2. Anonymous12 January 2023 at 05:24

    This book is really superb for starting design digital blocks using verilog HDL

    ReplyDelete
  3. Anonymous14 January 2023 at 08:40

    Awesome book keep it up

    ReplyDelete

Post a Comment

Popular posts from this blog

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to ev...
5 comments
Read more