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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Verilog HDL Coding Practice Question

 Hello Dear Readers, 

Today first time we will go to the pages part in which I will post differents types of practice questions that are more frequently asked by the interviewer.

Q-1:

See the verilog code I and II and explain what kind of dissimilarity is in between it and which code removes the glitches at the output and why.

Code-I:

module MUX2_1(input a,b,sel, output out);

wire sel_b,a1,b1;

not g1(sel_b,sel);

and g2(a1,a,sel_b);

and g3(b1,b,sel);

or  g4(out,a1,b1);

endmodule


Code-II:

module MUX2_1(input a,b,sel, output out);

wire sel_b,a1,b1,ab;

not g1(sel_b,sel);

and g2(a1,a,sel_b);

and g3(b1,b,sel);

and g4(ab,a1,b1);

or  g5(out,a1,b1,ab);

endmodule

Write down your answer in the comments and we will discuss it.

Q-2: In which conditions latches are created during RTL coding.


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Comments

  1. Anonymous5 November 2021 at 21:35

    Both code are same !!!

    ReplyDelete
    Replies
    1. ELECTRONICS AND COMMUNICATION HUBS5 November 2021 at 21:37

      Yes sorry now it has updated and thanks for feedback

      Delete
    2. Anonymous6 November 2021 at 00:15

      Ok sir now second code I think cancel the glitches.

      Delete
    3. Anonymous16 November 2021 at 21:02

      Answer of the second question is I think incomplete sensitivity list,case statement if we forgot any conditions etc ...

      Delete
  2. Anonymous6 November 2021 at 00:14

    First code because it is contain last or gate logic so output is avoid static hazards.

    ReplyDelete
  3. Anonymous6 November 2021 at 02:41

    First code is cancelled glitches

    ReplyDelete
  4. Anonymous6 November 2021 at 04:30

    First code avoid glitches

    ReplyDelete
  5. Anonymous6 November 2021 at 05:31

    Second code glitches free because of last AND gate logic.

    ReplyDelete
  6. ELECTRONICS AND COMMUNICATION HUBS16 November 2021 at 23:44

    First code cancel glitches and for second question if we not used all possibility inside case statements.

    ReplyDelete
  7. T MAHIPAL REDDY8 January 2022 at 21:05

    Latches are created during if any case is not declared and not even matches with default stmt

    ReplyDelete

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