Skip to main content

Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Post a Comment

Verilog HDL Coding Practice Question

 Hello Dear Readers, 

Today first time we will go to the pages part in which I will post differents types of practice questions that are more frequently asked by the interviewer.

Q-1:

See the verilog code I and II and explain what kind of dissimilarity is in between it and which code removes the glitches at the output and why.

Code-I:

module MUX2_1(input a,b,sel, output out);

wire sel_b,a1,b1;

not g1(sel_b,sel);

and g2(a1,a,sel_b);

and g3(b1,b,sel);

or  g4(out,a1,b1);

endmodule


Code-II:

module MUX2_1(input a,b,sel, output out);

wire sel_b,a1,b1,ab;

not g1(sel_b,sel);

and g2(a1,a,sel_b);

and g3(b1,b,sel);

and g4(ab,a1,b1);

or  g5(out,a1,b1,ab);

endmodule

Write down your answer in the comments and we will discuss it.

Q-2: In which conditions latches are created during RTL coding.


Connect with me 





Comments

  1. Anonymous5 November 2021 at 21:35

    Both code are same !!!

    ReplyDelete
    Replies
    1. ELECTRONICS AND COMMUNICATION HUBS5 November 2021 at 21:37

      Yes sorry now it has updated and thanks for feedback

      Delete
    2. Anonymous6 November 2021 at 00:15

      Ok sir now second code I think cancel the glitches.

      Delete
    3. Anonymous16 November 2021 at 21:02

      Answer of the second question is I think incomplete sensitivity list,case statement if we forgot any conditions etc ...

      Delete
  2. Anonymous6 November 2021 at 00:14

    First code because it is contain last or gate logic so output is avoid static hazards.

    ReplyDelete
  3. Anonymous6 November 2021 at 02:41

    First code is cancelled glitches

    ReplyDelete
  4. Anonymous6 November 2021 at 04:30

    First code avoid glitches

    ReplyDelete
  5. Anonymous6 November 2021 at 05:31

    Second code glitches free because of last AND gate logic.

    ReplyDelete
  6. ELECTRONICS AND COMMUNICATION HUBS16 November 2021 at 23:44

    First code cancel glitches and for second question if we not used all possibility inside case statements.

    ReplyDelete
  7. T MAHIPAL REDDY8 January 2022 at 21:05

    Latches are created during if any case is not declared and not even matches with default stmt

    ReplyDelete

Post a Comment

Popular posts from this blog

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...
Post a Comment
Read more

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more