Skip to main content

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a career in IC design/S
Post a Comment

Internship - SoC /IP Design at NXP India

Hello Dear Readers,

Currently, at NXP India vacancy for Internship - SoC /IP Design role. 

We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months.

Job Responsibility:

  • Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing.

  • Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design).

  • Design and verify digital and Mixed-signal IPs.

  • Document designs and present results.

Job Qualification:

  • Master student in electronic/computer engineering

  • Creative and positive mindset

  • Good knowledge on CMOS technologies

  • Great communication skills, interpersonal skills, teamwork skills and can-do attitude

  • Desire for a career in IC design/Semiconductor industry

  • Good knowledge on analog design is a plus.







Comments

Post a Comment

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_nets] setting maximum capacitance of 700fF on all nets. similarly, set_max
1 comment
Read more

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree
Post a Comment
Read more