Power Analysis in the VLSI Chip Design

 Hello Dear Readers, 

Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design.

The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded.

The output data from the power analysis flow guide the following SoC tape out release assessments: 

Total SoC power specification (average and standby leakage):

The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to evaluate the die attach material stress due to the different thermal expansion coefficients of the die, bump/bond metallurgy, encapsulation material, and package substrate. For mobile product applications, confirmation that the power specification is satisfied is crucial to achieving active and standby operating battery life targets. 

Peak power dissipation and peak power transient:

The peak power dissipation (along with the peak power transient) defines the limits on the package and system power and ground distribution network impedance to maintain voltages at the bumps that satisfy characterization assumptions. 

Local thermal hot spot identification and analysis:

Much as a thermal resistance model from the package to the enclosure is used for end-product thermal analysis, a thermal heat flow model for the die to the package is used for temperature analysis locally within the SoC. A high-power dissipation density within a small area of the die is denoted as a hot spot. At a hot spot, device temperatures may exceed the targeted limits used for cell characterization, invalidating timing analysis results. Temperature-dependent reliability failure mechanisms would be accelerated in these areas, as well. A hot spot may require the addition of a local thermsense circuit cell to signal to a central SoC power management unit that a throttling power state is required until the local temperature is reduced.

Note that several of these power analysis results criteria require detailed data about the specific location of the power dissipation on the die from the switching activity simulation data. The choice of simulation test cases is crucial to the accurate calculation of average and peak power dissipation. The activity data measured during RTL simulation is a guide to selecting test cases. However, RTL validation is typically focused on the coverage of unique system states and events rather than activity. An SoC project manager commonly allocates validation resources to compose power-centric test cases and allocates simulation licenses and compute resources to exercise these tests on the netlist-level model. Rather than provide SoC benchmark measurements, these power stress mark test cases do not necessarily reflect anticipated SoC workloads but are synthetically constructed to cover peak power dissipation.

Models For Switching Activity Power Dissipation:

The basic model for the calculation of the power dissipated by a net during a time interval is depicted in Fig. 1:

Fig. 1: Power dissipation model for a circuit switching transient 

During an output rising transition, the current through the pFET device stack charges the output load capacitance, and for a duration, while the input is in transition, it also sources the cross-over current through the nFET stack that was previously active. Conversely, during a falling output transition, the nFET stack discharges the load capacitance in combination with the cross-over current from pFET devices. Static leakage current flows in the cell through the active device stack to provide the subthreshold current of the off devices. The magnitude of the subthreshold current is strongly dependent on the input state, as shown in Fig. 2.

Fig. 2: The circuit subthreshold current is dependent on the input state

The static leakage current also includes the reverse-biased junction leakage from device source/drain nodes to the substrate (nFET) or well (pFET) potential. There is also a device gate leakage-to-channel current. With the addition of high-dielectric-constant (i.e., high-K) materials for the device gate in modern fabrication processes, the magnitude of gate leakage currents has dropped substantially. 

The basic model in Fig. 1, applies the sum of the interconnect load and fan-out gate capacitance to the cell output as C. For an average power calculation, a k-factor of 1 would be assigned to coupling capacitances; for peak power, a k-factor greater than 1 would normally be used. The average power dissipation associated with the current through the FET devices and the net capacitances is illustrated in Fig. 3.

Fig. 3: Illustration of the average power dissipation calculation

                                

Fig. 4: Short-circuit power during the switching

When dynamic power is analyzed as the switching component of power consumption, an instantaneous rise time is assumed, which ensures that only one of the transistors is ON. In practice, finite rise and fall times result in a direct current path between the supply and ground, GND, this exists for a short period during switching.

The cross-over current power dissipation is determined from the cell library characterization data, using the input and output slew results from the static timing analysis flow. The switching activity information from simulation test cases provided to the power analysis flow does not include the specific logical arcs for each cell that comprise the cell output signal activity factor; as a result, the power analysis flow needs to select a (conservative) cross-over power contribution, using the signal slew data from the STA flow results.  

The static leakage power is also derived from the cell library data. The cell characterization flow may record the input state-specific leakage current. Again, with only signal-switching activity information available, the power analysis flow needs to select a (conservative) leakage power measure from the cell model. If a specific power state leakage current calculation is appropriate, the power analysis flow accepts a set of logic signal values and duty cycle information to access the state-specific characterization data. 

The calculation of the estimated leakage power when logic cells are isolated from the power or ground distribution by sleepFETs is more complex, as shown in Fig. 4.

Fig. 4: Illustration of the leakage power dissipation calculation when the block is in the sleep state

A conservative model would assume that the internal rail will reach a potential equal to a device threshold voltage away from the other rail during the power-gated state and then calculate the device leakage current for the cumulative width of the sleepFETs at this drain-to-source voltage. The electrical model in Fig. 1 and the equation for average power dissipation use the total charge delivered to the load capacitance as the integral of the current through the power-dissipating active device stack. This model neglects the additional dissipation in the distributed interconnect resistance. With advanced process node scaling, there is indeed an additional resistive interconnect dissipation contribution that is significant, especially for (global) nets driven by high drive-strength cells, where the device R is no longer the dominant resistive element in the charging/discharging current path. The average power dissipation for each cell based on switching activity can thus be calculated as: 

Possible Interview Questions From the above Content:

1. What are the different powers sources in a CMOS inverter?
2. how power dissipation in CMOS varies with the skew of the clock
3. How tool calculate leakage power from the library data?
4. How many ways to calculate the switching activity of the design?
5. What do you mean by SAIF file and how it's generated from the ASIC design flow?
6. What is a VCD file? from which of the stage of ASIC design flow it has generated. What are the types of VCD file?
7. What is power integrity? Why it is important?
8. In the low power design which component of the power is mainly concerned.
9. What is the switching activity of the free-running clock?

EDA Company Tools:

1. Ansys: 

Ansys PowerArtist is the comprehensive RTL design-for-power platform of choice of leading low-power semiconductor companies for early power analysis and reduction. PowerArtist includes physically-aware RTL power accuracy, interactive power debugging, analysis-driven power reduction, unique metrics for tracking power efficiency and vector coverage, rapid power profiling of real workloads, and seamless enablement of RTL-to-physical power grid integrity.

https://www.ansys.com/products/semiconductors/ansys-powerartist

2. Cadence:

Cadence Joules RTL Design Studio allows RTL designers to rapidly get early and accurate insight into the physical design effects of power, performance, area, and congestion (PPAC). Front-end designers can locate problems in the design layout, trace them to the source code, and automatically give actionable guidance to improve RTL for better PPAC. Simultaneously, implementation engineers benefit from this early debugging because they can now allocate resources to fix issues that cannot be fixed at the RTL level. 

https://semiwiki.com/eda/cadence/4889-a-new-unified-power-solution-at-all-levels/

3. Synopsys:

PrimePower RTL power estimation leverages the Predictive Engine from Synopsys' RTL Architect™ product to provide RTL designers with fast, scalable, and accurate power estimation for early analysis of RTL blocks, subsystems, and full-SoCs. PrimePower RTL enables designers to analyze, explore, and optimize their RTL with confidence, improving power, and energy efficiency, and shortening the design cycle.

During implementation and signoff, PrimePower provides accurate gate-level power analysis reports for SoC designers to make timely design optimizations and achieve power targets. Supported power analysis includes average power, peak power, glitch power, clock network power, dynamic and leakage power, and multi-voltage power; with activity from RTL and gate-level vectors from simulation, emulation, and vectorless analysis. By closely integrating with PrimeTime, the golden industry standard for timing and signal integrity analysis and signoff, PrimePower expands the PrimeTime solution to deliver accurate dynamic and leakage power analysis and signoff for gate-level designs.

https://alvinrolling.github.io/opt/PrimePower/

4. Siemens:

PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power estimation for both RTL and Gate-level designs, early power checks to quickly find power issues during RTL development, and clock and memory gating to optimize the design for power.

https://eda.sw.siemens.com/en-US/ic/powerpro/

Connect with me 

1.Linkedln

2.Instagram

3.Facebook

4.WhatsApp