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Showing posts from September, 2022

Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Best Courses For RTL/FPGA Engineer Profiles

  Hello Dear Readers, Currently, after succeeding up to this today, I will start new NPTEL courses per VLSI and ECE branch job profiles. So let's start with today's RTL/FPGA engineer profiles courses. 1. HARDWARE MODELING USING VERILOG: Coordinators: PROF. INDRANIL SENGUPTA  Department of Computer Science and Engineering IIT Kharagpur INTENDED AUDIENCE: CSE, ECE, EE  PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++  INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx COURSE OUTLINE: The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.  ABOUT INSTRUCTOR:   Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. He joined the Indian Instit
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Design Engineer, PCIE at NVIDIA Bangalore

   Hello Dear Readers, Currently at Nvidia Bangalore vacancy for Design Engineer, PCIE role. NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world’s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and unde
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Advisory Physical Design Engineer at IBM Bangalore

Hello Dear Readers,   Currently, at IBM Bangalore vacancy for an Advisory Physical Design Engineer role. Introduction: As a Hardware Developer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role and Responsibilities: Responsible for high-performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor planning, placement, and routing. Close the design to meet timing, power budget, and area. Implement ECOs to address functional bugs and timing violations. Team player with good problem-solving and communication skills. Required Technical and Professional Expertise: Good knowledge and hands on experience in physical design methodology which include logic synthesis, placement, clock tree synthesis, routing . Should be knowledgeable in physic
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Physical Design Engineer at Texas Instruments

  Hello Dear Readers, Currently, at Texas Instruments vacancy for a Physical Design Engineer role. Overview: You would be Interacting closely with digital/analog designers and completely owning area-power-timing optimization, design closure and signoff of signal chain IPs and top level of Ethernet PHYs targeted at Automotive and Industrial markets. These designs and IPs (0.5 Million to 5 million gates; 100MHz – 2.5GHz ; 65nm/28nm CMOS) and are part of TI’s growing portfolio of IEEE compliant robust, low-power Ethernet PHYs with deterministic low latency and industry leading PTP/AVB/MACSEC for the industrial and automotive markets (including advanced single pair and multi-gigabit standards). The role provides excellent challenges and opportunities to innovate and grow within and beyond the core domain through functional rotations within the Ethernet product team. Industry Experience and Qualification: 1-5 years’ experience in physical design Master’s / Bachelor’s / Diploma in Electronic
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