Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...
Hello Dear Readers,
Currently, after succeeding up to this today, I will start new NPTEL courses per VLSI and ECE branch job profiles. So let's start with today's RTL/FPGA engineer profiles courses.
1. HARDWARE MODELING USING VERILOG:
Coordinators:
PROF. INDRANIL SENGUPTA
Department of Computer Science and Engineering IIT Kharagpur
INTENDED AUDIENCE: CSE, ECE, EE
PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++
INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx
COURSE OUTLINE:
The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.
ABOUT INSTRUCTOR:
Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering (CSE) from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in 1988, in the Department of CSE, where he is presently a full Professor. He had been the former Heads of the Department of Computer Science and Engineering and also the School of Information Technology of the Institute. He has over 28 years of teaching and research experience. He has guided 22 Ph.D. students and has more than 200 publications to his credit in international journals and conferences.
COURSE PLAN:
Week 01: Introduction to digital circuit design flow (3 hours)
Week 02: Verilog variables, operators, and language constructs (2 hours)
Week 03: Modeling combinational circuits using Verilog (2 hours)
Week 04: Modeling sequential circuits using Verilog (3 hours)
Week 05: Verilog test benches and design simulation (2 hours)
Week 06: Behavioral versus structural design modeling (2 hours)
Week 07: Miscellaneous modeling issues: pipelining, memory, etc. (2 hours)
Week 08: Processor design using Verilog (4 hours)
2. SYSTEM DESIGN THROUGH VERILOG:
Coordinators:
PROF. SHAIK RAFI AHAMED
Department of EEE
IIT Guwahati
INTENDED AUDIENCE: CSE, ECE, EE
PRE-REQUISITES: Basic concepts in digital circuit design, Familiarity with a programming language like C or C++
INDUSTRIES APPLICABLE TO: Intel, Cadence, Mentor Graphics, Synopsys, Xilinx
COURSE OUTLINE:
A comprehensive resource on Verilog HDL for beginners and experts, large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.
ABOUT INSTRUCTOR:
Prof. Shaik Rafi Ahamed is a professor with more than 20 years teaching experience. He had taught Digital design, including Verilog, nearly 10 times for undergraduate students at IIT Guwahati and other institutions. He have published several papers in reputed Journals like IEEE, Elsevier, IET and Springer.
COURSE PLAN:
Week-1: Introduction to Verilog
Week-2: Gate-level modeling
Week-2: Gate-level modeling
Week-3: Behavioral modeling I
Week-4: Behavioral modeling II
Week-4: Behavioral modeling II
Week-5: Data flow modeling
Week-6: Switch level modeling
Week-7: Synthesis of combinational logic using Verilog
Week-8: Synthesis of sequential logic using Verilog
Week-8: Synthesis of sequential logic using Verilog
3. Hardware Security
Coordinators:
PROF. DEBDEEP MUKHOPADHYAY
Department of Computer Science and Engineering
IIT Kharagpur
INTENDED AUDIENCE: CSE, ECE, EE (PG And UG)
PRE-REQUISITES: Cryptography
INDUSTRIES APPLICABLE TO: TexasInstruments/BOSCH/DRDO/HAL/Wipro/CDAC/ISRO/Rambus/Intel/Qualcomm/Synopsys/IBM/Microsoft/Cadence/SecureIC/Riscure/Mentor Graphics/Xilinx/Nvidia
COURSE OUTLINE:
This course will address security threats on modern hardware design, manufacturing, installation, and operating practices. In particular, the threats would be shown to be relevant at scales ranging from a single user to an entire nation's public infrastructure. Through theoretical analyses and relevant practical world case studies, the threats would be demonstrated, and then state-of-the-art defense techniques would be described. The course would borrow concepts from diverse fields of study such as cryptography, hardware design, circuit testing, algorithms, and machine learning.
ABOUT INSTRUCTOR:
Prof. Debdeep Mukhopadhyay is currently a full Professor at the Department of Computer Science and Engineering, IIT-Kharagpur, India.At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Embedded Security and Side Channel Attacks( [ http://cse.iitkgp.ac.in/resgrp/seal/ | http://cse.iitkgp.ac.in/resgrp/ seal/ ] ) . Prior to this he worked as an associate Professor at IIT Kharagpur, visiting scientist at NTU Singapore, a visiting Associate Professor of NYU-Shanghai, Assistant Professor atIIT-Madras, and as Visiting Researcher at NYU Tandon-School-of-Engineering, USA. He holds a PhD, an MS, and a B. Tech from IIT Kharagpur, India.
COURSE PLAN:
Week 1: Introduction, Finite Fields, AES Hardware, S-Box
Week 2: Algorithm to Hardware, Case Study on ECC, Intro to ECC
Week 3: Implementation of ECC, Hardware Design of ECC
Week 4: Introduction to Side Channel Analysis
Week 5: Advanced SCA, Introduction to Fault Attacks
Week 6: Advanced Fault Attacks, Algebraic Fault Analysis
Week 7: Countermeasures-I
Week 8: Countermeasures-II
Week 9: Introduction to PUFs, Designs on FPGAs, Machine Learning of PUFs
Week 10: Design-for-Testability for Cryptographic Designs
Week 11: Protocols, Challenges, Introduction to Micro-architectural attacks
Week 12: Advanced Micro-architectural attacks, Hardware monitoring for malware using Hardware Performance Counters
Week 3: Implementation of ECC, Hardware Design of ECC
Week 4: Introduction to Side Channel Analysis
Week 5: Advanced SCA, Introduction to Fault Attacks
Week 6: Advanced Fault Attacks, Algebraic Fault Analysis
Week 7: Countermeasures-I
Week 8: Countermeasures-II
Week 9: Introduction to PUFs, Designs on FPGAs, Machine Learning of PUFs
Week 10: Design-for-Testability for Cryptographic Designs
Week 11: Protocols, Challenges, Introduction to Micro-architectural attacks
Week 12: Advanced Micro-architectural attacks, Hardware monitoring for malware using Hardware Performance Counters
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Thanks bro for post really apprieciate your effort
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