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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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SRAM/Memory CAD Engineer at Qualcomm

 Hello Dear Readers,

Qualcomm Bangalore currently has a vacancy for an SRAM/Memory CAD Engineer.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Roles and Responsibilities:

· Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows.

· Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation.

· Determine key areas where automation and leading methodologies can help improve PPA.

· Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience.

Preferred qualifications:

· Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA.

· Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.).

· Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc.

· Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows.

· Good understanding of stdcell or memory design fundamentals.

· Excellent partner collaborating with design team in flow debug and support.

· Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.)

· Tool knowledge in any of these is a plus – nanotime, xa/spectre, liberate, primelib, totem


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