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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Evolution of Logic Design and Its Abstractions

  Hello Dear Readers, Today, I have summarized the evolution of logic design and two abstractions of the system design flow that has been discussed. During the year 1958, Jack Kilby, a young electrical engineer at Texas Instrument figured out how to place the circuit elements, transistors, resistors, and capacitors, on a small piece of Germanium. But prior to the year 1958, many more revolutionized ideas were published and conceptualized. Gottfried Leibniz was a famous mathematician and philosopher from Germany and he redefined the binary number system during the year 1676–1679. After the successful redefinition of number systems, the famous mathematician George Boole during the year 1854 invented the Boolean algebra and the revolution of the digital logic design set into motion. The actual invention of the prototype transistor model during the year 1946–1947 at Bell Labs by Shockley, Bardeen, Brattain had revolutionized the use of semiconductor in switching theory and for design of ch
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The Design For Testability (DFT) and its necessity

  Hello Dear Readers, Today In this post I will explain DFT and its necessity in VLSI. In the practical ASIC design, the DFT is used to find out various kinds of faults in the design. For FPGA designs this step is excluded. The necessity of DFT is for early detection of the faults in the design using scan chain insertions. The functional abstraction of defects is called a fault and the abstraction of the fault is the system-level error. Physical testing is carried out after manufacturing of chip to understand the fabrication-related issues or faults. The defects in the design can be physical or electrical. Physical defects are due to silicon or defective oxide. Electrical defects are short, open, transistor defects and changes in the threshold voltage. A few of the faults in the design are following  1. Stuck at faults: Stuck at one or Stuck at zero  2. Memory faults or pattern-sensitive faults  3. Bridging faults  4. Crosspoint faults  5. Delay faults  The testing process is the proce
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Verilog : always@ Blocks

  Hello Dear Readers, Today In this post I will explain various flavors of the always@ blocks. There are normally two ways that we normally noticed in different Verilog codes that always@( * ) and always@(posedge Clock) block. always@ blocks are used to describe events that should happen under certain conditions. always@ blocks are always followed by a set of parentheses, a begin , some code, and an end . Program 1 shows a skeleton always@ block.  In Program 1 , The contents of the always@ block, namely elements describe elements that should be set when the sensitivity list is “satisfied.” For now, just know that when the sensitivity list is “satisfied,” the elements inside the always@ block are set/updated. They are not otherwise. Elements in an always@ block are set/updated sequentially and in parallel, depending on the type of assignment used. There are two types of assignments: <= (non-blocking) and = (blocking) . Non-blocking assignments happen in parallel. In other
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Restoring And Non Restoring Division Algorithms Using Verilog HDL

  Hello Dear Readers, Today In this post I have implemented Restoring Division Algorithm Using Verilog HDL. So I have followed this   One video from Tutorial Point Youtube Channel   So go through it before Verilog code. start means the start of the division; busy indicates that the divider is busy (cannot start a new division); ready indicates that the quotient and remainder are available, and the  count is the output of a counter that is used to control the iterations of the division. Verilog Code(Restoring): module divider_32(a,b,start,clk,reset,q,r,busy,ready,count); input [31:0] a; // dividend input [15:0] b; // divisor input start; // start input clk,reset; // clk,reset output [31:0] q; // quotient output [15:0] r; // remainder output reg busy; // busy output reg ready; // ready output [4:0] count; // counter reg [31:0] reg_q; reg [15:0] reg_r; reg [15:0] reg_b; reg [4:0] count; wire [16:0] sub_out = {reg_r,reg_q[31]} - {1'b0,reg_b}; // sub wi
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