The Design For Testability (DFT) and its necessity

 Hello Dear Readers,

Today In this post I will explain DFT and its necessity in VLSI.

In the practical ASIC design, the DFT is used to find out various kinds of faults in the design. For FPGA designs this step is excluded. The necessity of DFT is for early detection of the faults in the design using scan chain insertions. The functional abstraction of defects is called a fault and the abstraction of the fault is the system-level error. Physical testing is carried out after manufacturing of chip to understand the fabrication-related issues or faults. The defects in the design can be physical or electrical. Physical defects are due to silicon or defective oxide. Electrical defects are short, open, transistor defects and changes in the threshold voltage. A few of the faults in the design are following 

1. Stuck at faults: Stuck at one or Stuck at zero 

2. Memory faults or pattern-sensitive faults 

3. Bridging faults 

4. Crosspoint faults 

5. Delay faults 

The testing process is the process of test pattern generation, test pattern application and output evaluation. 

Generally, the test flow includes the following: 

1. Identify the target faults 

2. Test generation 

3. Fault Simulation 

4. Testability 

5. DFT 

Design For Testability (DFT):

The DFT is required to reduce the defect level in the design. Consider the following design; in this design, it is not possible to give the test input so the design is not testable. The DFT uses the concept of controllability and observability. 

The key steps are

1. RTL design 

2. Simulation 

3. Synthesis 

4. Insert scan chain 

5. Layout 

If every data input of the register need to be forced to the known value during the test, then the design is controllable. Observability indicates the ability to observe the node at the primary output. The de-sign needs to be controllable and observable. As shown in the following Fig-1, the design input of comb_logic1 is controllable and the output from comb_logic3 is observable. But comb_logic1 and comb_logic2 are not observable. So for the detection of faults, it is essential to make comb_logic1, comb_logic2, and comb_logic3 controllable as well as observable.

Figure-1

The basic DFT techniques are Ad-HOC DFT and Structured DFT. The structured DFT includes the scan-based DFT which is again classified as MUX - based DFT and level–sensitive, element-based DFT. Another structured DFT technique is MBIST and LBIST. JTAG is used for boundary-scan. The basic MUX-based technique is described below. • MUX-based scan cell The MUX-based scan cell is shown below Fig-2, and it has additional inputs as Test_data, Scan_en. The MUX is inserted at the input of the D flip-flop and during testing Scan_en=1 the D input is Test_data. During normal operation, the Scan_en=0 and Data_in can pass through the combinational logic to the D input. Thus, the following cell works both in the test and normal modes. The clk can be scan_clk during the test mode.

Figure-2

MUX-based scan chain: 

The normally used method is the insertion of the scan by using MUX logic. MUX-based scan cell shown in the above figure is used to replace the sequential elements from the design. Depending on the requirements the design team decides whether to use the partial scan method or the full scan method. In the partial scan method, few of the sequential elements are replaced by the MUX-based scan cell. In the full scan method, all the sequential elements are replaced by the MUX-based scan cell. Due to scan insertion, the area and timing of the design have a significant impact. Scan insertion increases the area of the design and due to added MUX-based logic even affects the timing of the design. The following example shows the scan chain using MUX-based scan cells. Most of the time, the partial scan is recommended if area and timing is the constraint but this reduces overall fault coverage. If the full scan is used then it increases area and has a significant impact on timing but this improves overall fault coverage.

Figure-3

Scan Design rules:

Following are a few of the scan design rules that need to be considered: 

1. Generated clocks in the design: There should not be generated clocks in the design as they are not controllable 

2. Combinational feedback loop: There should not be any combinational loop in the design as it creates issues in the timing analysis and hence it is essential to break the combinational loop 

3. Gated clocks: Gated clocks need to be avoided as they are not controllable 

4. Asynchronous Control signals: There should not be any internally generated asynchronous control signals 

5. Do not mix the positive and negative edge-triggered flip-flops 

6. Avoid the use of latches in the design 

7. If shift registers are used then do not replace them by using scan enabled flipflops but only ensure the enable control 

8. Do not use the clock input as data 

9. Bypass the memories during DFT

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