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Showing posts from December, 2022

VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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SoC Verification Engineer at Truechip

  Hello Dear Readers,   Currently, at Truechip vacancy for an SoC Verification Engineer role. Post: SoC Verification Engineer Required Experience: 1 to 3 years Location: Bangalore, Delhi NCR, Hyderabad Openings: 8-10 Education: BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Worked on IP level verification environment: 1 to 3 years of experience Good experience with Verilog, System Verilog and UVM Experience with verification for protocols like AXI or AHB Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB Excellent Team Player Experience in SOC Verification Experience in Formal verification Experience in verification of automotive protocols If interested please share your profile to:  sweta.srivastava@truechip.net Connect with me  1.Linkedln 2.Instagram 3.Facebook 4.WhatsApp  
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IP Design Methodology of VLSI Semi-Custom Chip Design

  Hello Dear Readers,   Today in this post I will provide some deep insight into IP design methodology.  The design of an IP core entails developing and releasing a set of models for subsequent SoC methodology flow integration. These models are described in the following sections.  1. Functional Model for Logic Validation: The functional IP model is first compiled into the SoC simulation environment. The model source is usually provided as part of the IP license either in the hard or soft IP, typically in a hardware description language (HDL) format. For hard IP, for added security of the intellectual property, a compiled binary is licensed, with a set of EDA simulation tool application program interface functions to initialize, exercise, and query the behavior.  An HDL model can be developed at different levels of functional abstraction— that is, a logic gate–level netlist, a register transfer–level module, or a model utilizing higher-level semantics. For ...
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Physical Design Engineer (All Levels) at InSemi Technology

  Hello Dear Readers,   Currently at InSemi Technology vacancy for a Physical Design Engineer role. Preferred Education: B.Tech/M.Tech Area of Expertise: Good knowledge of VLSI process and device characteristics Experience doing physical design targeted to the 7nm/16nm FinFet process Good knowledge of cell libraries’ various views and models Good understanding of static timing analysis (STA), EM/IR, and sign-off. Strong hands-on experience with Chip Level / Sub-chip level floor planning, > partition, pin assignment, Power planning, Bump Planning, Pad Ring Creation, > Block level physical implementation, timing closure, physical verification, Chip level integration of different sub-blocks, and custom macros/IPs, Timing, IR/EM analysis and closure, Physical Verification – block and chip level EDA Tool Expertise: Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre,LEC, etc Good software and scripting skills (Python, tcl) Good communication skills and the a...
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Field-Programmable Gate Arrays Engineer at Centum T&S

  Hello Dear Readers, Currently, at Centum T&S vacancy for a Field-Programmable Gate Arrays Engineer role. About the job: Centum T&S is a Business unit of Centum Electronics Group offers a wide range of electronic and embedded systems design engineering services to Global Customers to help them realize complex products and sub systems. Centum T&S is an Electronics Design Center of Excellence, designing for mission critical projects in Aerospace/Space, Transportation, Medical Electronics, Defense Electronics etc. It has other design centers in the France, USA, Canada & Germany. The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager. What You'll...
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SYSTEM VIP Verification Engineer at Cadence Design System

  Hello Dear Readers, Currently, at Cadence Design System vacancy for a SYSTEM VIP Verification Engineer role. Job Description:  Good experience on SOC level performance analysis and System level scenarios validation Hands-on DDR interface, peripherals Ethernet, DMA transfer and System level I/O coherency testing Worked on the AXI/Ace/Other Amba protocols debug and C test case development Overall hands on exp on SOC DV flows and test case development for ARM based SOCs Advantage: Good knowledge in software languages (C++/PYTHON/JAVA/JAVA Script) Customer support experience Knowledge in scripting Perl /shell scripting or similar languages ·         Educational Qualification :  BE/BTech or ME/ M.Tech  Graduate wit.h Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses. If interested please share your profile to:  rajesha@cadence.com ...
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Verification Engineer - On contract at MediaTek Bangalore

   Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for Verification Engineer - On contract role. About the job: 1-year contract. Rollover contract. 0-2 years of experience in   SV / UVM. Ability to trace, debug and root cause failures in the RTL code. Must be familiar with waveform debug tools like Verdi and Mentor’s visualizer. Cognizant with   SV   functional coverage, assertions. Implement SV coverage points and assertions. Familiar with AMBA protocols (AXI, AHB, APB). Desirable : Perl scripting, experience with bus matrix verification (NOC), familiarity with protocols like PCIe SDIO and experience with cross-geo communication. Company Overview: MediaTek is a global fabless semiconductor company that enables more than 2 billion consumer products a year. We are a market leader in developing tightly-integrated, power-efficient systems-on-chip (SoC) for mobile devices, home entertainment, network and connectivity, automated driving, ...
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Intern - Physical Design at Global Foundries

  Hello Dear Readers,   Currently at Global Foundries vacancy for Intern - Physical Design role. GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. Introduction: GLOBALFOUNDRIES is looking for a highly motivated experienced engineer to work on the GTO (Global Tapeout Operations) team as a Frame Design Automation Engineer located in Bangalore, India.  The successful candidate will enjoy a variety of assignments that will include developing automation to generate electrical structures that are also known as Process Control Monitoring (PCM) structures, contributing to test and development efforts for our ...
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