Hello Dear Readers, Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
Hello Dear Readers,
Currently, at Truechip vacancy for an SoC Verification Engineer role.
Required Experience: 1 to 3 years
Location: Bangalore, Delhi NCR, Hyderabad
Openings: 8-10
Education: BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)
Worked on IP level verification environment:
- 1 to 3 years of experience
- Good experience with Verilog, System Verilog and UVM
- Experience with verification for protocols like AXI or AHB
- Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB
- Excellent Team Player
- Experience in SOC Verification
- Experience in Formal verification
- Experience in verification of automotive protocols
- If interested please share your profile to: sweta.srivastava@truechip.net
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