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YAML in Semiconductor EDA: From Configuration Language to Reusable Design-Flow Methodology

Hello Dear Readers,   Today in this post, I will provide some deep insight about yaml langauge for CAD flow developments with detailed examples. YAML is not a programming language in the same sense as Python, Tcl, C++, or Verilog. It is primarily a human-readable data serialization/configuration language . In semiconductor EDA, that distinction is important because YAML generally describes what a flow should do , while Python/Tcl/Shell and the EDA tools execute the flow . The official YAML specification describes it as a data serialization language designed to be human-friendly and portable across programming languages. For the semiconductor angle, this becomes particularly interesting because YAML can act as a configuration layer between design methodology and EDA implementation . Frameworks such as Hammer explicitly use YAML/JSON configuration and an intermediate representation to standardize information exchanged between design, technology, and tool plugins. 1. Introduction M...
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SoC Verification Engineer at Truechip

 Hello Dear Readers, 

Currently, at Truechip vacancy for an SoC Verification Engineer role.

Post: SoC Verification Engineer
Required Experience: 1 to 3 years
Location: Bangalore, Delhi NCR, Hyderabad
Openings: 8-10
Education: BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication)

Worked on IP level verification environment:

  • 1 to 3 years of experience
  • Good experience with Verilog, System Verilog and UVM
  • Experience with verification for protocols like AXI or AHB
  • Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB
  • Excellent Team Player
  • Experience in SOC Verification
  • Experience in Formal verification
  • Experience in verification of automotive protocols








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  1. Anonymous30 December 2022 at 02:24

    Hi bro I am selected in this post. Thanks for your effort 🙂🙂🙂🙂

    ReplyDelete

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