Hello Dear Readers, Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
Hello Dear Readers,
Currently, at Cadence Design System vacancy for a SYSTEM VIP Verification Engineer role.
Job Description:
Good experience on SOC level performance analysis and System level scenarios validation
Hands-on DDR interface, peripherals Ethernet, DMA transfer and System level I/O coherency testing
Worked on the AXI/Ace/Other Amba protocols debug and C test case development
Overall hands on exp on SOC DV flows and test case development for ARM based SOCs
Advantage:
- Good knowledge in software languages (C++/PYTHON/JAVA/JAVA Script)
- Customer support experience
- Knowledge in scripting Perl /shell scripting or similar languages
Educational Qualification :
BE/BTech or ME/M.Tech Graduate wit.h Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses.
If interested please share your profile to: rajesha@cadence.com
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