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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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SYSTEM VIP Verification Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Design System vacancy for a SYSTEM VIP Verification Engineer role.

Job Description: 

Good experience on SOC level performance analysis and System level scenarios validation
Hands-on DDR interface, peripherals Ethernet, DMA transfer and System level I/O coherency testing
Worked on the AXI/Ace/Other Amba protocols debug and C test case development
Overall hands on exp on SOC DV flows and test case development for ARM based SOCs
Advantage:
  • Good knowledge in software languages (C++/PYTHON/JAVA/JAVA Script)
  • Customer support experience
  • Knowledge in scripting Perl /shell scripting or similar languages
·        
Educational Qualification : 

BE/BTech or ME/M.Tech Graduate wit.h Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses.

If interested please share your profile to: rajesha@cadence.com  


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