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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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SYSTEM VIP Verification Engineer at Cadence Design System

 Hello Dear Readers,

Currently, at Cadence Design System vacancy for a SYSTEM VIP Verification Engineer role.

Job Description: 

Good experience on SOC level performance analysis and System level scenarios validation
Hands-on DDR interface, peripherals Ethernet, DMA transfer and System level I/O coherency testing
Worked on the AXI/Ace/Other Amba protocols debug and C test case development
Overall hands on exp on SOC DV flows and test case development for ARM based SOCs
Advantage:
  • Good knowledge in software languages (C++/PYTHON/JAVA/JAVA Script)
  • Customer support experience
  • Knowledge in scripting Perl /shell scripting or similar languages
·        
Educational Qualification : 

BE/BTech or ME/M.Tech Graduate wit.h Computer Science/Electronics & Communication/Electrical & Electronics/VLSI engineering or any other equivalent courses.

If interested please share your profile to: rajesha@cadence.com  


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