Skip to main content

Product Engineer II at Cadence Design Systems

Hello Dear Readers, Cadence Design Systems has a vacancy for a Product Engineer II role. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage: The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recog...
Post a Comment

Field-Programmable Gate Arrays Engineer at Centum T&S

 Hello Dear Readers,

Currently, at Centum T&S vacancy for a Field-Programmable Gate Arrays Engineer role.

About the job:

Centum T&S is a Business unit of Centum Electronics Group offers a wide range of electronic and embedded systems design engineering services to Global Customers to help them realize complex products and sub systems. Centum T&S is an Electronics Design Center of Excellence, designing for mission critical projects in Aerospace/Space, Transportation, Medical Electronics, Defense Electronics etc. It has other design centers in the France, USA, Canada & Germany.

The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager.


What You'll Do:

  • Design and implementation of FPGAs collaborating with peer engineers and global stakeholders
  • Participate in the architecture definition, implementation and verification phases
  • Provide reliable estimates for the work to be performed and identify technical risks
  • Ensure performance with expected quality and within schedule; achieve and surpass the productivity norms of the global organization, driving continuous improvement
  • Develop and implement block level RTL, perform synthesis and achieve timing closure.
  • Results-orientation: Focus on Customers, provide quality deliverables on time, within estimated effort with high quality
  • Characteristics for a design engineering services business: establish trust, responsive to change/adaptability; learn continuously, proactive, positive & joyful.

Qualifications:

  • Bachelor's degree in Computer Science, Electrical OR Electronics Engg (or related field)
  • Signal processing, Experience in Network protocols like Ethernet, RCF*, UDP/IPMicro AFDX, ARINC664 or A664, Wireshark, PCI Express, 1G/10G Ethernet or SERDES high-speed serial links, AXI/AHB, I2C, SPI, RS422.
  • Strong knowledge in RTL(FPGA/SOC/IP) design architecture & design.
  • Coding experience in VHDL or Verilog (1+ years)
  • Experienced in PCI Express, 1G/10G Ethernet or SERDES high-speed serial links, AXI/AHB, I2C, SPI, RS422, ARINC 429/717/818, MIL 1553, etc.
  • Experience in memory control interfaces such as Flash, DDR2/3, etc.
  • Expertise in trouble-shooting and debugging FPGA implementations
  • Experience in building test benches and bus functional models for FPGA simulation
  • Experience in writing scripts to drive simulation and synthesis tools
  • Excellent documentation, reporting and communication skills.
  • Excellent analytical skills.
  • Hands-on experience on D0254 process is highly preferable 

If interested please share your profile to:dilipt@centumtns.com


Connect with me 

Labels:

Comments

Post a Comment

Popular posts from this blog

SDC (Synopsys Design Constraints) contents part 4

Today, we will be discussing the remaining constraints mentioned in the SDC, which pertain to timing exceptions and design rules. This is the final part of the SDC contents. This is going to be interesting, especially with multicycle paths. Take time to read and try to comprehend. 10. set_max_transition     By setting max transition value, our design checks that all ports and pins are meeting the specified limits mentioned in SDC. If these are not satisfied then timing report will give DRVs (design rule violations) in terms of slack. This is specified as               set_max_transition 0.5  UBUF1/A setting maximum limit of 500ps on pin A of Buffer1. 11. set_max_capacitance     This is same as max transition, setting the maximum capacitance value. if our design not meeting this value then violation will occur. This will also reports under design rule violations in terms of slack.     set_max_capacitance 0.7 [all_...
1 comment
Read more

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Enc...
Post a Comment
Read more

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or...
Post a Comment
Read more