Skip to main content

Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal

Field-Programmable Gate Arrays Engineer at Centum T&S

 Hello Dear Readers,

Currently, at Centum T&S vacancy for a Field-Programmable Gate Arrays Engineer role.

About the job:

Centum T&S is a Business unit of Centum Electronics Group offers a wide range of electronic and embedded systems design engineering services to Global Customers to help them realize complex products and sub systems. Centum T&S is an Electronics Design Center of Excellence, designing for mission critical projects in Aerospace/Space, Transportation, Medical Electronics, Defense Electronics etc. It has other design centers in the France, USA, Canada & Germany.

The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager.


What You'll Do:

  • Design and implementation of FPGAs collaborating with peer engineers and global stakeholders
  • Participate in the architecture definition, implementation and verification phases
  • Provide reliable estimates for the work to be performed and identify technical risks
  • Ensure performance with expected quality and within schedule; achieve and surpass the productivity norms of the global organization, driving continuous improvement
  • Develop and implement block level RTL, perform synthesis and achieve timing closure.
  • Results-orientation: Focus on Customers, provide quality deliverables on time, within estimated effort with high quality
  • Characteristics for a design engineering services business: establish trust, responsive to change/adaptability; learn continuously, proactive, positive & joyful.

Qualifications:

  • Bachelor's degree in Computer Science, Electrical OR Electronics Engg (or related field)
  • Signal processing, Experience in Network protocols like Ethernet, RCF*, UDP/IPMicro AFDX, ARINC664 or A664, Wireshark, PCI Express, 1G/10G Ethernet or SERDES high-speed serial links, AXI/AHB, I2C, SPI, RS422.
  • Strong knowledge in RTL(FPGA/SOC/IP) design architecture & design.
  • Coding experience in VHDL or Verilog (1+ years)
  • Experienced in PCI Express, 1G/10G Ethernet or SERDES high-speed serial links, AXI/AHB, I2C, SPI, RS422, ARINC 429/717/818, MIL 1553, etc.
  • Experience in memory control interfaces such as Flash, DDR2/3, etc.
  • Expertise in trouble-shooting and debugging FPGA implementations
  • Experience in building test benches and bus functional models for FPGA simulation
  • Experience in writing scripts to drive simulation and synthesis tools
  • Excellent documentation, reporting and communication skills.
  • Excellent analytical skills.
  • Hands-on experience on D0254 process is highly preferable 

If interested please share your profile to:dilipt@centumtns.com


Connect with me 

Comments

Popular posts from this blog

Apprenticeship CAI at MediaTek Bangalore

Hello Dear Readers,   Currently at MediaTek Bangalore vacancy for an Apprenticeship CAI role. Job Description: B.Tech degree in Electrical/Electronics Engineering with a strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid understanding of STA and timing constraints. Experienced in working on advanced process nodes (16nm). Strong expertise in Physical Verification to debug LVS/DRC issues at the block level. Requirement: B.Tech degree in Electrical/Electronics Engineering with strong educational background in Digital circuit design Experience in physical design of high performance design with frequencies > 2 Ghz. Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains. Strong skills with Cadence Encounter. Solid

Power Analysis in the VLSI Chip Design

  Hello Dear Readers,   Today in this series of posts I will provide some deep insight into Power Analysis in the VLSI Chip Design. The power analysis flow calculates (estimates of) the active and static leakage power dissipation of the SoC design. This electrical analysis step utilizes the detailed extraction model of the block and global SoC layouts. The active power estimates depend on the availability of switching factors for all signals in the cell netlist. Representative simulation test cases are applied to the netlist model, and the signal value change data are recorded. The output data from the power analysis flow guide the following SoC tape out release assessments:  Total SoC power specification (average and standby leakage): The specification for SoC power is critical for package selection and is used by end customers for thermal analysis of the product enclosure. In addition to the package technology selection, the SoC power dissipation is used to evaluate the die attach ma

IC Physical Design (PnR) at Ulkasemi

Hello Dear Readers,   Ulkasemi  has a vacancy for an IC Physical Design (PnR) role. Job Overview: As a full-time Trainee Engineer, the individual will be working on IC Physical Design implementation from RTL to GDSII to create design databases ready for manufacturing with a special focus on power, performance & area optimization with next-generation state-of-the-art process technologies. Job Responsibilities: Perform physical design implementation which includes Floor planning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Logic Equivalence checks Timing analysis, physical & electrical verification, driving the sign-off closure meeting schedule, and design goals Develop flow, methodologies, and automation scripts for various implementation steps Follow the instructions, compile documents, prepare deliverables, and report to the team lead Should remain up to date with the latest technology trends Educational Qualification:   B.Sc/M.Sc   in EEE or equivalent degree