Verilog : always@ Blocks

 Hello Dear Readers,

Today In this post I will explain various flavors of the always@ blocks. There are normally two ways that we normally noticed in different Verilog codes that always@( * ) and always@(posedge Clock) block.

always@ blocks are used to describe events that should happen under certain conditions. always@ blocks are always followed by a set of parentheses, a begin, some code, and an end. Program 1 shows a skeleton always@ block. 

In Program 1, The contents of the always@ block, namely elements describe elements that should be set when the sensitivity list is “satisfied.” For now, just know that when the sensitivity list is “satisfied,” the elements inside the always@ block are set/updated. They are not otherwise. Elements in an always@ block are set/updated sequentially and in parallel, depending on the type of assignment used. There are two types of assignments: <= (non-blocking) and = (blocking).

Non-blocking assignments happen in parallel. In other words, if an always@ block contains multiple <= assignments, which are literally written in Verilog sequentially, you should think of all of the assignments being set simultaneously. For example, consider Program 2.

Program 2 specifies a circuit that reads “when the sensitivity list is satisfied, B gets A’s value, C gets B’s old value and D gets C’s old value.” The key here is that C gets B’s old value, etc..

Blocking assignments happen sequentially. In other words, if an always@ block contains multiple = assignments, you should think of the assignments being set one after another. For example, consider Program 3.

Program 3 specifies a circuit that reads “when the sensitivity list is satisfied, B gets A, C gets B, and D gets C.” But, by the time C gets B, B has been set to A. Likewise, by the time D gets C, C has been set to B, which, as we stated above, has been set to A. This always@ block turns B, C, and D into A. Blocking assignments are used when specifying combinational logic.

always@(posedge Clock) (“always at the positive edge of the clock”) or always@(negedge Clock) (“always at the negative edge of the clock”) blocks are used to describe Sequential Logic or Registers. Only <= (non-blocking) assignments should be used in an always@(posedge Clock) block. Never use = (blocking) assignments in always@(posedge Clock) blocks. Only use always@(posedge Clock) blocks when you want to infer an element(s) that changes its value at the positive or negative edge of the clock. For example, consider Figure 1, a recreation of Program 2 that uses a posedge Clock as its sensitivity list. Figure 1 is also known as a shift register. The completed always@ block is shown in Program 4.

always@(*) blocks are used to describe Combinational Logic or Logic Gates. Only = (blocking) assignments should be used in an always@(*) block. Never use <= (non-blocking) assignments in always@(*) blocks. Only use always@(*) block when you want to infer an element(s) that changes its value as soon as one or more of its inputs change. 

Always use ‘*’ (star) for your sensitivity list in always@(*) blocks. The sensitivity list specifies which signals should trigger the elements inside the always@ block to be updated. For example, given 3 wires A, B, and C, we can create an and gate through Program 5, and shown graphically in Figure 2.

Program 5 specifies that “when A or B change values, update the value of every element inside the always@(*) block. In this case, the only element inside the always@(*) block is C, which in this case is assigned the and of A and B. A very common bug is to introduce an incomplete sensitivity list. See Program 6 for two examples of incomplete sensitivity lists.

In Program 6, the first example produces an and gate that only updates its output C when A changes. If B changes, but A does not change, C does not change because the always@(A) block isn’t executed. Likewise, the second example produces an and gate that doesn’t react to a change in A. Incomplete sensitivity lists are almost NEVER what you want! They introduce very hard-to-find bugs. As such, we use always@(*). The ‘*’ is shorthand for always@(A or B) in our examples. In other words, ‘*’ sets the sensitivity list to any values that can have an impact on a value(s) determined by the always@( * ) block. ‘*’ provides a bug-free shorthand for creating complete sensitivity lists. 

Pitfalls:

The following are some easy-to-make mistakes in Verilog that can have a dramatic [and undesired] effect on a circuit.

Consider the shift register from Figure 1. If you place = assignments inside of an always@(posedge Clock) block to produce the shift register, you instead get the parallel registers shown in Figure 3 and Program 7. You might also get one register, whose output is tied to B, C, and D. Both possible outcomes are equivalent. These circuits make sense, but don’t create shift registers! (As shift registers are a common construct, we assume that you wanted to create a shift register).

The opposite example (shown in Program 8), where we place <= assignments inside of always@( * ) is less pronounced. In this case, just consider what type of circuit you want to create: do you want all statements to be executed in parallel or in ‘sequence’? In the always@( * ), the distinction between <= and = is sometimes very subtle, as the point of always@ ( * ) is to trigger at indefinite times (unlike the very definite posedge Clock). We recommend = in conjunction with always@( * ) to establish good convention (as = was originally meant to be associated with combinational logic).

Lastly, a very subtle point that perhaps has the potential to cause the most frustration is latch generation. If you don’t assign every element that can be assigned inside an always@( * ) block every time that always@( * ) block is executed, a latch (similar to a register but much harder to work with in FPGAs) will be inferred for that element. This is never what you want and is a terrible place for bugs. As this is subtle, it is somewhat hard to visualize. Consider Program 9.

In Program 9, A and C are both assigned in at least one place inside the always@ block. A is always assigned at least once. This is because the first line of the always@ block specifies a default value for A. This is a perfectly valid assignment. It ensures that A is always assigned with each execution of the always@ block. C on the other hand is not always assigned. When Trigger = 1’b1, the if statement ‘executes’ and both A and C get set. If Trigger = 1’b0, however, the if is skipped. A is safe, as it was given a default value on the first line of the always@ block. C on the other hand doesn’t get assigned at all when this happens. As such, a latch is inferred for C. The erroneous circuit depicted in Program 9 is shown in Figure 4.

To fix this problem, we must make sure that C gets set every time the always@ block is ‘executed.’ A simple way to force this is to add another default value, depicted in Program 10 and shown in Figure 5.

Default values are an easy way to avoid latch generation, however, will sometimes break the logic in a design. As such, other ways of ensuring that each value always gets set are going to be worth looking into. Typically, they involve proper use of the Verilog else statement and other flow constructs. Know that setting a reg to itself is not an acceptable way to ensure that the reg always gets set. For example, C = C; injected into the top of the always@( * ) block in Program 9 will not suppress latch generation. In every ‘execution’ of an always@( * ) block, each value that is assigned in at least one place must be assigned to a non-trivial value during every ‘execution’ of the always@( * ) block.

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