Hello Dear Readers, At HPE Bangalore, there is a vacancy for a Physical Design Engineer role. This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Aruba is an HPE Company, and a leading ...
Hello Dear Readers,
Currently, at Texas Instruments vacancy for a Physical Design Engineer role.
Overview:
You would be Interacting closely with digital/analog designers and completely owning area-power-timing optimization, design closure and signoff of signal chain IPs and top level of Ethernet PHYs targeted at Automotive and Industrial markets. These designs and IPs (0.5 Million to 5 million gates; 100MHz – 2.5GHz ; 65nm/28nm CMOS) and are part of TI’s growing portfolio of IEEE compliant robust, low-power Ethernet PHYs with deterministic low latency and industry leading PTP/AVB/MACSEC for the industrial and automotive markets (including advanced single pair and multi-gigabit standards). The role provides excellent challenges and opportunities to innovate and grow within and beyond the core domain through functional rotations within the Ethernet product team.
Industry Experience and Qualification:
- 1-5 years’ experience in physical design
- Master’s / Bachelor’s / Diploma in Electronics/Electrical/Computer-Science
Hands on Domain Knowledge:
- Synthesis, DFT insertion, LEC
- Place & Route
- Floor planning, power grid creation for sea-of-gate designs w/ memories
- Static and Dynamic IR drop analysis and optimization
- Resolving routing congestions and DRCs
- LVS closure
- Crosstalk analysis
- Timing
- Good understanding of STA concepts, SDC constructs, design margins.
- Clock Tree Synthesis; Constraints to guide the CTS tool; Debugging
- Creation and review of Timing Constraints (jointly with RTL designers)
- Multi-Mode * Multi-Corner Timing Closure
- Manual analysis/debug of CTS and STA issues
- Metal-only ECOs (for functionality and timing)
- Tool Scripting for sanity checks, reporting, debug and automation
- Ability to root cause timing and clock issues (eg. constraints, structural aspects)
- Experience in following would be big plus
- DFT, MBIST/PBIST, ATPG Pattern generation
- LINT/CDC
- Toolchain:
- Knowledge of Cadence toolchain is preferred (Genus, Innovus, Tempus, Voltus)
- Scripting languages (Tcl, Shell/Perl/Python)
Minimum requirements:
- Bachelor's degree in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering or related field
- Cumulative 3.0/4.0 GPA or higher
Preferred qualifications:
- Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
- Strong verbal and written communication skills
- Ability to quickly ramp on new systems and processes
- Demonstrated strong interpersonal, analytical and problem-solving skills
- Ability to work in teams and collaborate effectively with people in different functions
- Ability to take the initiative and drive for results
- Strong time management skills that enable on-time project delivery
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