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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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Physical Design Engineer at Texas Instruments

 Hello Dear Readers,

Currently, at Texas Instruments vacancy for a Physical Design Engineer role.

Overview:

You would be Interacting closely with digital/analog designers and completely owning area-power-timing optimization, design closure and signoff of signal chain IPs and top level of Ethernet PHYs targeted at Automotive and Industrial markets. These designs and IPs (0.5 Million to 5 million gates; 100MHz – 2.5GHz ; 65nm/28nm CMOS) and are part of TI’s growing portfolio of IEEE compliant robust, low-power Ethernet PHYs with deterministic low latency and industry leading PTP/AVB/MACSEC for the industrial and automotive markets (including advanced single pair and multi-gigabit standards). The role provides excellent challenges and opportunities to innovate and grow within and beyond the core domain through functional rotations within the Ethernet product team.

Industry Experience and Qualification:

  • 1-5 years’ experience in physical design
  • Master’s / Bachelor’s / Diploma in Electronics/Electrical/Computer-Science

Hands on Domain Knowledge:

    • Synthesis, DFT insertion, LEC
    • Place & Route
      • Floor planning, power grid creation for sea-of-gate designs w/ memories
      • Static and Dynamic IR drop analysis and optimization
      • Resolving routing congestions and DRCs
      • LVS closure
      • Crosstalk analysis
    • Timing
      • Good understanding of STA concepts, SDC constructs, design margins.
      • Clock Tree Synthesis; Constraints to guide the CTS tool; Debugging
      • Creation and review of Timing Constraints (jointly with RTL designers)
      • Multi-Mode * Multi-Corner Timing Closure
      • Manual analysis/debug of CTS and STA issues
      • Metal-only ECOs (for functionality and timing)
      • Tool Scripting for sanity checks, reporting, debug and automation
      • Ability to root cause timing and clock issues (eg. constraints, structural aspects)
    • Experience in following would be big plus
      • DFT, MBIST/PBIST, ATPG Pattern generation
      • LINT/CDC
    • Toolchain:
      • Knowledge of Cadence toolchain is preferred (Genus, Innovus, Tempus, Voltus)
      • Scripting languages (Tcl, Shell/Perl/Python)

Minimum requirements:

  • Bachelor's degree in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering or related field
  • Cumulative 3.0/4.0 GPA or higher

Preferred qualifications:

  • Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
  • Strong verbal and written communication skills
  • Ability to quickly ramp on new systems and processes
  • Demonstrated strong interpersonal, analytical and problem-solving skills
  • Ability to work in teams and collaborate effectively with people in different functions
  • Ability to take the initiative and drive for results
  • Strong time management skills that enable on-time project delivery

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