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Carry Lookahead Adder Design And Implementation of Generic Parametrized Adder Using Verilog HDL

 Hello Dear Readers,

Today In this post I have designed a carry-lookahead adder design and implemented its parametrized version using Verilog HDL and analysis that design for the desire output. First of all, I have designed CLA based on the theory described in the below video of the Neso Academy.
     


Verilog Code:
module add (a, b, c, g, p, s); // adder and g, p
input a, b, c; // inputs: a, b, c;
output g, p, s; // outputs: g, p, s;
assign s=a ^ b ^ c; // output: sum of inputs
assign g = a & b; // output: carry generator
assign p = a | b; // output: carry propagator
endmodule

module gp (g,p,c_in,g_out,p_out,c_out); // carry generator, carry propagator
input [1:0] g, p; // lower level 2-set of g, p
input c_in; // lower level carry_in
output g_out,p_out,c_out; // higher level g, p, carry_out
assign g_out = g[1] | p[1] & g[0]; // higher level carry generator
assign p_out = p[1] & p[0]; // higher level carry propagator
assign c_out = g[0] | p[0] & c_in; // higher level carry_out
endmodule

module cla_2 (a, b, c_in, g_out, p_out, s); // 2-bit carry lookahead adder
input [1:0] a, b; // inputs: a, b
input c_in; // input: carry_in
output g_out, p_out; // outputs: g, p
output [1:0] s; // output: sum
wire [1:0] g, p; // internal wires
wire c_out; // internal wire
// add (a, b, c, g, p, s); // generates g,p,s
add a0 (a[0], b[0], c_in, g[0], p[0], s[0]); // add on bit 0
add a1 (a[1], b[1], c_out, g[1], p[1], s[1]); // add on bit 1
// gp (g, p, c_in, g_out, p_out, c_out); // higher level g,p
gp gp0 (g, p, c_in, g_out, p_out, c_out); // higher level g,p
endmodule

module cla_4 (a,b,c_in,g_out,p_out,s); // 4-bit carry lookahead adder
input [3:0] a, b; // inputs: a, b
input c_in; // input: carry_in
output g_out, p_out; // outputs: g, p
output [3:0] s; // output: sum
wire [1:0] g, p; // internal wires
wire c_out; // internal wire
cla_2 a0 (a[1:0],b[1:0],c_in, g[0],p[0],s[1:0]); // add on bits 0,1
cla_2 a1 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); // add on bits 2,3
gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p
endmodule

module cla_8 (a,b,c_in,g_out,p_out,s); // 8-bit carry lookahead adder
input [7:0] a, b; // inputs: a, b
input c_in; // input: carry_in
output g_out, p_out; // outputs: g, p
output [7:0] s; // output: sum
wire [1:0] g, p; // internal wires
wire c_out; // internal wire
cla_4 a0 (a[3:0],b[3:0],c_in, g[0],p[0],s[3:0]); // add on bits 0-3
cla_4 a1 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); // add on bits 4-7
gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p
endmodule

module cla_16 (a,b,c_in,g_out,p_out,s); // 16-bit carry lookahead adder
input [15:0] a, b; // inputs: a, b
input c_in; // input: carry_in
output g_out, p_out; // outputs: g, p
output [15:0] s; // output: sum
wire [1:0] g, p; // internal wires
wire c_out; // internal wire
cla_8 a0 (a[7:0], b[7:0], c_in, g[0],p[0],s[7:0]); // add on bits 0-7
cla_8 a1 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); // add on bits 8-15
gp gp0 (g,p,c_in, g_out,p_out,c_out); // higher level g,p
endmodule

module CLA_32(a,b,c_in,g_out,p_out,s);
input [31:0] a, b; // inputs: a, b
input c_in; // input: carry_in
output g_out, p_out; // outputs: g, p
output [31:0] s; // output: sum
wire [1:0] g, p; // internal wires
wire c_out; // internal wire
cla_16 a0 (a[15:0], b[15:0], c_in, g[0],p[0],s[15:0]); // + bits 0-15
cla_16 a1 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); // + bits 16-31
gp gp0 (g,p,c_in,g_out,p_out,c_out);
endmodule

module cla32 (a,b,ci,s); // 32-bit carry lookahead adder, no g, p outputs
input [31:0] a, b; // inputs: a, b
input ci; // input: carry_in
output [31:0] s; // output: sum
wire g_out, p_out; // internal wires
CLA_32 cla (a, b, ci, g_out, p_out, s); // use cla_32 module
endmodule

Simulational Results:




Parametrized Version Verilog Code:
module carry_lookahead_adder(A,B,S,Cout,Cin);
    parameter N = 4;
    
    input [N-1:0]A,B;
    input Cin;
    output [N-1:0]S;
  output Cout;

    wire [N-1:0]P, G ;
    wire [N:0]C;
    propagate_generate #(.N(N)) M1(.A(A), .B(B), .P(P), .G(G));
    carry_generate #(.N(N)) M2 (.P(P), .G(G), .C(C), .Cin(Cin));

    assign S = P ^ C;
    assign Cout = C[N];

endmodule


module propagate_generate(A,B,P,G);
    parameter N = 4;
    input [N-1 :0] A,B;
    output [N-1 :0]P,G;

    assign P = A^B;
    assign G = A&B;

endmodule


module carry_generate(P,G,C,Cin);
    parameter N = 4;
    input [N-1:0]P,G;
  input Cin;
    output [N:0]C;
    assign C[0] =Cin;
    genvar i;
  generate for(i=1;i<=N;i=i+1) begin
        assign C[i] = G[i-1] | (P[i-1]&C[i-1]);
    end
    endgenerate

endmodule


Test Bench Verilog Code:

module tb;
    reg [2:0]A,B;
    wire [2:0]S;
    reg Cin;
    wire Cout;

    carry_lookahead_adder #(.N(3)) DUT(.A(A), .B(B), .S(S), .Cout(Cout), .Cin(Cin));


    task load(input [2:0]a,b, input c); begin
        A = a;
        B = b;
      Cin = c;    
    end
    endtask

    integer i , j,k;
    initial begin
        $dumpfile ("carry_lookahead_adder.vcd");
        $dumpvars (0, tb);  
        for (k=0;k<2;k=k+1) begin
            for (i=0; i<8 ; i=i+1) begin
                for(j=0;j<8;j=j+1) begin
                    load(i,j,k);
                    #10;
                end
            end
        end
        $finish;
    end
    initial $monitor("A = %b, B = %b, Cin = %b, Cout = %b, Sum = %b",A,B,Cin,Cout,S);

endmodule

Simulational Results:


If you want to implement its entire RTL to GDSII then refer to the below articles series.




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