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Verification Engineer or Senior Verification Engineer SOC at MIPS India

Hello Dear Readers, Currently, at MIPS India  vacancy for a Verification Engineer or Senior Verification Engineer SOC role. We are seeking an experienced Verification Engineer or Senior Verification Engineer SOC. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification, and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. You will: Take full ownership and drive verification efforts to closure Work closely with designers and architects to understand specifications at unit/top level Understand use cases and develop functional test plans Develop directed tests written in C, Assembly, and SystemVeri
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ARM Assembly Language Practice Question And Answer Part-4

 Hello Dear Readers, 

Today in this post I will provide some basics to advanced ARM's assembly language practice QA part-4, I have used the Keil tool for code writing.

Q-1). Write an assembly language program that performs a mode change by modifying the contents of the CPSR. 

  a. The mode you should change to is user mode, and you have to modify the mode field of CPSR by the value of 0x10. 

  b. This assumes that the current mode is a privileged mode such as supervisor mode.

Code:

; program which changes the microprocessor mode 

masking equ 0x1f 

user_mode equ 0x10 

 area change, code, readonly

entry 

 MRS R0,CPSR; read the status of the microprocessor 

 BIC R0, R0,#masking; apply the masking bit 

 ORR R0,R0,#user_mode ; set the mode user_mode 

 MSR CPSR_C,R0 ; written back with control_field_mask 

 END 

Output:


Q-2). Write an assembly language program that generates Software Interrupt (SVC) to perform an operation either addition or multiplication of 3 registers based on value passed to SVC Number. Store result at memory location 0x5000.

Code:

; program to implement SWI for the two operation 

 area intruppt, code, readonly 

entry 

LDR PC,=Reset_Handler 

LDR PC,=Udef_Addr 

LDR PC,=SVC_Handler 

LDR PC,=PAbt_Addr 

LDR PC,=DAbt_Addr 

NOP ; reserved vector 

LDR PC,=IRQ_Addr 

LDR PC,=FIQ_Addr 

Reset_Handler 

  LDR R0,=0 

  LDR SP,=0X8000 

   B main 

SVC_Handler

  STMFD SP!,{R0-R12,LR} 

   LDR R10,[LR,#-4] ; FETCH OPCODE OF THE SWI 

   BIC R10,R10,#0XFF000000 

   CMP R10,#01 

   BLEQ SWI_ADD ; call subroutinue 

   CMP R10,#02 

   BLEQ SWI_MUL 

main 

    LDR R0,=2 

    LDR R1,=2 

    LDR R2,=2 

    SWI 02 

STOP B STOP 

SWI_ADD 

    ADD R3,R1,R2 

    ADD R4,R0,R3 

    LDR R5,=0X5000 

    STR R4,[R5] 

    LDMFD SP!,{R0-R12,PC} 

    stop B stop 

SWI_MUL 

   MUL R3,R1,R2 

   MUL R4,R0,R3 

    LDR R5,=0X5000 

    STR R4,[R5] 

    LDMFD SP!,{R0-R12,PC} 

    EXIT B EXIT 

Udef_Addr 

PAbt_Addr 

DAbt_Addr 

IRQ_Addr 

FIQ_Addr 

 END

Output:


Q-3). Write an assembly language program for the sorting (Ascending Order) of five numbers stored at 0x4000 using subroutine.

Code:

; program of the wring subroutinue for the sorting 5 numbers

loc EQU 0X4000 

loc1 EQU 0X5000 ; here i have used another memory location just for calculation 

 AREA sort, CODE ,READONLY 

ENTRY 

START 

  LDR SP, =0X4100 

  LDR R0, =loc

  LDR R1, =loc1 

  LDMIA R0!, {R2-R6}

  STMIA R1!, {R2-R6} 

   BL num_asc 

   LDMDB R1!, {R2-R6} 

   STMDB R0!, {R2-R6} 

   STOP B STOP 

num_asc 

  STMIA SP!, {LR} 

  LDR R3, =0X6 

AGAIN 

  SUBS R3, R3, #1

  BEQ OVER

   LDMDB R1!, {R5} 

   LDR R4, =0X6 

   MOV R2, R1 

DO 

   SUBS R4, R4, #1 

    BEQ AGAIN 

    LDMDB R2!, {R6}

    CMP R5, R6 

     BMI DO 

     STR R5, [R2] 

     STR R6, [R1] 

     MOV R5, R6 

      B DO 

OVER 

     LDMDB SP!, {PC} 

 END

Output:


Q-4). Write an assembly language program that generates Software Interrupt (SVC) to perform an operation GCD or LCM of 2 registers based on the value passed to SVC Number. Store result at memory location 0x4fff.

Code:

area gcd_lcm, CODE, READONLY 

ENTRY 

ldr pc,=main 

ldr pc,=SVC_Handler 

SVC_Handler 

   stmfd sp!,{r0-r12,lr}

   ldr r10,[lr,#-4] 

    bic r10,r10,#0xff000000 

    cmp r10,#01 

    bleq gcd 

    cmp r10,#02 

    bleq lcm 

main 

    ldr sp,=0x4000 

    ldr r0,=8 

    ldr r1,=2 

    mov r2,r1 

    mov r3,r0 

    swi 02 

   STOP B STOP 

gcd 

   CMP R1, R0 

   SUBSGT R1, R1, R0 

   SUBSLT R0, R0, R1 

   bne gcd 

   ldr r5,=0x4fff 

   strb r0,[r5] 

   ldmfd sp!,{r0-r12,pc} 

   stop B stop 

lcm 

    CMP R1, R0 

     SUBSGT R1, R1, R0 

     SUBSLT R0, R0, R1 

     bne lcm 

     muls r4,r2,r3 

     ldr r6,=0x0

label 

    subs r4,r4,r0 

    add r6,r6,#1 

     bgt label 

      ldr r5,=0x4fff

      strb r6,[r5] 

      ldmfd sp!,{r0-r12,pc} 

 exit b exit 

end

Output:


Q-5). Translate each of the following pseudo-code statements into a sequence of ARM assembly language instructions. Assume x and y are integers and x is in R1 and y is in R2.

Code:

AREA pseudo,CODE,READONLY 

ENTRY 

  ldr r0,data 

  ldr r1,[r0] 

  ldr r2,[r0,#4] 

  cmp r1,#9 

   bls loop_1 

   mov r1,#0 

    cmp r2,#9

    bls loop_2 

    mov r2,#0

    b nr

 loop_2 

    adds r2,r2,#1 

    stop b stop

loop_1 

    adds r1,r1,#1

nr 

data dcd 0X4000 

END 

Output:


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