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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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Silicon CPU/ SOC Verification Engineer at Rivos Inc

   Hello Dear Readers,

Currently at Rivos Bangalore vacancy for a Silicon CPU/ SOC Verification Engineer role.

Positions are open for full-time and Co-op/internship in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal.

We are looking for all levels of talent, from entrance to advanced level of experience.


Responsibilities:

  • Work closely with architecture and RTL designers on verifying the functionality correctness of the design
  • Reviewing Architecture and Design Specifications
  • Develop test plans and test environments
  • Develop tests in assembly, C/C++, or vectors according to test plans
  • Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
  • Develop checkers in SystemVerilog or C-base transactors to verify the design
  • Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
  • Debugging failures, running simulations, tracking bugs
  • Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions


Requirements:

  • In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
  • Sophisticated knowledge of SystemVerilog.
  • Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
  • Basic knowledge of formal verification methodology is a plus.
  • Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
  • Ability to work well in a team and be productive under aggressive schedules.


Education and Experience:

  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.


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Comments

  1. Anonymous21 November 2022 at 03:22

    Thanks for posting fresher opportunity

    ReplyDelete
  2. Anonymous21 November 2022 at 04:39

    Amazing opportunity and it's product based right?

    ReplyDelete

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