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Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
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Std cell Circuit Design & Characterization Engineer at Cognitive Design Technology Pvt Ltd

Hello Dear Readers,

Currently, at Cognitive Design Technology Pvt Ltd vacancy for a Std cell Circuit Design & Characterization role.

Specific Responsibilities:

  • Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
  • Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
  • Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products.
  • Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team.
  • Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new circuit design methodologies.


Requirement :

  • Proficiency in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio
  • Solid understanding of FinFET technology and its impact on standard cell library design and characterization.
  • Familiarity with circuit and layout design, static timing analysis (STA) and power analysis methodologies.
  • Strong analytical skills and attention to detail for data analysis and problem-solving.
  • Advanced process nodes (e.g., 16nm, 12nm, 6nm or below) is highly desirable.
  • Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.
  • Exceptional candidates with a Master’s degree will be considered.

Apply Here


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