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ASIC Physical Design Engineer at HPE

  Hello Dear Readers, At HPE Bangalore, there is a vacancy for a Physical Design Engineer role. This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Aruba  is an HPE Company, and a leading ...
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Std cell Circuit Design & Characterization Engineer at Cognitive Design Technology Pvt Ltd

Hello Dear Readers,

Currently, at Cognitive Design Technology Pvt Ltd vacancy for a Std cell Circuit Design & Characterization role.

Specific Responsibilities:

  • Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
  • Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
  • Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products.
  • Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team.
  • Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new circuit design methodologies.


Requirement :

  • Proficiency in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio
  • Solid understanding of FinFET technology and its impact on standard cell library design and characterization.
  • Familiarity with circuit and layout design, static timing analysis (STA) and power analysis methodologies.
  • Strong analytical skills and attention to detail for data analysis and problem-solving.
  • Advanced process nodes (e.g., 16nm, 12nm, 6nm or below) is highly desirable.
  • Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.
  • Exceptional candidates with a Master’s degree will be considered.

Apply Here


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