Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
Hello Dear Readers,
Currently, at Cognitive Design Technology Pvt Ltd vacancy for a Std cell Circuit Design & Characterization role.
Specific Responsibilities:
- Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
- Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
- Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products.
- Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team.
- Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new circuit design methodologies.
Requirement :
- Proficiency in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio
- Solid understanding of FinFET technology and its impact on standard cell library design and characterization.
- Familiarity with circuit and layout design, static timing analysis (STA) and power analysis methodologies.
- Strong analytical skills and attention to detail for data analysis and problem-solving.
- Advanced process nodes (e.g., 16nm, 12nm, 6nm or below) is highly desirable.
- Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.
- Exceptional candidates with a Master’s degree will be considered.
Comments
Post a Comment