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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...
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Std cell Circuit Design & Characterization Engineer at Cognitive Design Technology Pvt Ltd

Hello Dear Readers,

Currently, at Cognitive Design Technology Pvt Ltd vacancy for a Std cell Circuit Design & Characterization role.

Specific Responsibilities:

  • Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
  • Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
  • Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products.
  • Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team.
  • Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new circuit design methodologies.


Requirement :

  • Proficiency in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio
  • Solid understanding of FinFET technology and its impact on standard cell library design and characterization.
  • Familiarity with circuit and layout design, static timing analysis (STA) and power analysis methodologies.
  • Strong analytical skills and attention to detail for data analysis and problem-solving.
  • Advanced process nodes (e.g., 16nm, 12nm, 6nm or below) is highly desirable.
  • Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.
  • Exceptional candidates with a Master’s degree will be considered.

Apply Here


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