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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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SDC(Synopsys Design Constraints) contents part 3

 Dear readers, today we will be discussing the IO-related constraints mentioned in the SDC file. The reason for defining the commands in the SDC file and their significance.

STA cannot check the paths which are not constrained. Therefore, all paths must be constrained.

5. set_input_delay

    This tells us how much time data will be delayed with respect to the clock to reach the input port of our design. That is the delay used by the external logic. So, the designer can estimate how much time is left for internal logic to meet the targets.

For example, The delay at the input port defined by the combined delay of clock to Q delay of UFF0 and combinational delay. This delay is defined with respect to the CLKA.


This is specified as

        set_input_delay 1.5 -clock CLKA  [get_ports INP]

Input delay can be specified for worst case slow (max) corner and best case fast (min) corner.

            create_clock     -name CLKA   -period 10  [get_ports CLK]

             set_input_delay  -clock CLKA    -max 1.5 [get_ports INP]

             set_input_delay  -clock CLKA    -min 0.8 [get_ports INP]

Here, by specifying the external inputs the available setup time for internal logic is (10-1.5) 8.5ns at the slow corner and (10-0.8) 9.2ns at the fast corner. Thus, available time to reliably capture the data  is the minimum time 8.5ns. If max, min are not mentioned then take the same value for both corners. 

"-clock_fall"  option is used for input delay with respect to falling edge. if nothing mentioned then it is for rising edge of the clock.

6. set_output_delay

    Output delay specifies how much time external logic needs to meet the requirements, so the designer can calculate how much time left to meet the internal timing targets. Output delay specifies with respect to the capture clock. CLKQ specifies available time between launch and capture clock.

Example


The total delay of Tc2+Tsu is our output delay. This can be specified as
            
                        set_output_delay  5     -clock CLKQ [get_ports OUT]

Similar to input delay, output delay also can be specified for both min and max. Max path delay is max(Tc2)+Tsu and min path delay specified as min(Tc2 - Th).

                create_clock    -period 15   [get_ports CLKQ]
                set_output_delay  -max 6.2   -clock CLKQ [get_ports OUT]
                set_output_delay  -min -0.2   -clock CLKQ [get_ports OUT]


External attributes

7. set_drive, set_driving_cell

    Both of these used to model the external drive strength that drives the input port of a block. This is used to calculate the transition of the first cell in our block and also used to compute the delay from input port to the first cell. If these attributes are not specified, then by default all inputs are assumed to have infinite drive strength,

set_drive 100  [all_inputs]

Specifies the drive resistance of 100 ohms at all inputs. Resistance value 0ohm means drive strength is infinite.

set_driving_cell   -lib_cell AND    -library milkyway [get_ports INP] 

INP port is driven by AND cell from milkyway library. 

 One red flag about set_driving_cell specification is that incremental delay due to capacitive load is included as an additional delay at the input port. An alternative approach for this is specify transition using set_input_transition.

8. set_input_transition.

It is easy way to specify the slew on the input port.

set_input_transition  0.6   [get_ports INP].

9. set_load

    It Specifies the capacitive load on output port. By default load on output port is 0. one need to specify the load driven by the output port.

set_load 10 [get_ports OUT]

sets the load capacitance of 10pF on OUT port 

set_load 0.5 [get_nets UCNET/NET4] 

 Sets the net load capacitance to be 0.5pF.

That's all for today guys. We will meet in the next topic which is design rule related constraints and clock exceptions. That will be the last post in the SDC contents. 

Thank you so much for your love. Keep reading our blogs and share with your friends so that all could learn. 

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