Modelling of Binary Encoding, Gray Encoding and One-hot encoding FSM using Verilog HDL

Hello Dear Readers, 

Today, I will explain how binary, gray, one-hot encoding FSM design using Verilog HDL.

1). Binary Encoding:

Binary encoding style can be used if the area requirement is a constraint on the design. In this encoding style state parameters for the binary encoding are represented in the binary format.

Two-Bit Binary Up-Counter FSM:

Two-bit binary counter FSM is described below, the number of states is equal to 4 and it needs four state variables ‘s0,’ ‘s1,’ ‘s2,’ and ‘s3.’ The number of flip-flops used to represent the functionality of the counter is equal to 2. The state transition table and the state transition diagram is shown in Fig.1 and Fig.2. The transition from one state to another state occurs on the positive edge of the clock. The default state is ‘s0’ and it is the reset state. So outcome is Moore machine as the output is a function of the current state only.

Fig.1 State Transition Table

Fig.2 State Diagram

Verilog Code:

module binary_count(clk,rst,y_out);

input clk,rst;

output reg [1:0]y_out;

parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;

reg [1:0]current_state,next_state;

// state logic definition

always @(posedge clk or negedge rst)

begin

  if(~rst)

     current_state<=s0;

  else

     current_state<=next_state;

end

// next state logic definition

always @(current_state)

case (current_state)

s0:next_state=s1;

s1:next_state=s2;

s2:next_state=s3;

s3:next_state=s0;        

default: next_state=s0;

endcase

//output logic definition

always @(current_state)

case(current_state)

s0:y_out=2'b00;

s1:y_out=2'b01;

s2:y_out=2'b10;

s3:y_out=2'b11;

default: y_out=2'b00;

endcase

endmodule

Simulational Results:

Fig.3 

2). Gray Encoding:

The Gray encoding style can be used if the area requirement is a constraint on the design. In this encoding style, state parameters are represented in the Gray format. 

Two-Bit Gray Counter FSM:

Two-bit Gray counter FSM is described below, the number of states is equal to 4 and it needs four state variables ‘s0,’ ‘s1,’ ‘s2,’ and ‘s3.’ The number of flip-flops used to represent the functionality of the counter is equal to 2. The state transition table and the state transition diagram is shown in Fig.4 and Fig.5. The transition from one state to another state occurs on the positive edge of the clock. The default state is ‘s0’ and it is the reset state. So the outcome is Moore machine as the output is a function of the current state only.

Fig.4 Gray Up-Counter State Table

Fig.5 State Diagram

Verilog Code:

module gray_count(clk,rst,y_out);

input clk,rst;

output reg [1:0]y_out;

parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;

reg [1:0]current_state,next_state;

// state logic definition

always @(posedge clk or negedge rst)

begin

  if(~rst)

     current_state<=s0;

  else

     current_state<=next_state;

end

// next state logic definition

always @(current_state)

case (current_state)

s0:next_state=s1;

s1:next_state=s3;

s3:next_state=s2;

s2:next_state=s0;        

default: next_state=s0;

endcase

//output logic definition

always @(current_state)

case(current_state)

s0:y_out=2'b00;

s1:y_out=2'b01;

s3:y_out=2'b11;

s2:y_out=2'b10;

default: y_out=2'b00;

endcase

endmodule

Simulational Results:

Fig.5 

3). One-Hot Encoding:

Two-bit Gray counter FSM is described below, the number of states is equal to 4 and it needs four state variables ‘s0,’ ‘s1,’ ‘s2,’ and ‘s3.’ The number of flip-flops used to represent the functionality of the counter is equal to 4. The state transition table is shown in Fig.6. The transition from one state to another state occurs on the positive edge of the clock. The default state is ‘s0’ and it is the reset state. So the outcome is Moore machine as the output is a function of the current state only.

Fig.6 State table for One-Hot Encoding FSM

Verilog Code:

module onehot_count(clk,rst,y_out);

input clk,rst;

output reg [1:0]y_out;

parameter s0=4'b0001,s1=4'b0010,s2=4'b0100,s3=4'b1000;

reg [3:0]current_state,next_state;

// state logic definition

always @(posedge clk or negedge rst)

begin

  if(~rst)

     current_state<=s0;

  else

     current_state<=next_state;

end

// next state logic definition

always @(current_state)

case (current_state)

s0:next_state=s1;

s1:next_state=s2;

s2:next_state=s3;

s3:next_state=s0;        

default: next_state=s0;

endcase

//output logic definition

always @(current_state)

case(current_state)

s0:y_out=2'b00;

s1:y_out=2'b01;

s3:y_out=2'b11;

s2:y_out=2'b10;

default: y_out=2'b00;

endcase

endmodule

Simulational Results:

Fig.7 

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