Skip to main content

Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Post a Comment

Multiplexer Verilog Code

Hello Dear Readers,

Here I have giving Verilog code of 32-bit Multiplexer which is a common digital system block. A multiplexer selects an input from multiple inputs. The following code implements a 32-bit 2-to-1 multiplexer as well as a 4-to-1 multiplexer using a function. The [31:0] denotes a bus that has 32 bits. So Let's Start it code.

Verilog Code:

1) Multiplexer Using Dataflow Level:

module mux2to1 (a0,a1,s,y); // multiplexer, 32 bits 
 // inputs, 32 bits
input [31:0] a0, a1;    
  // input selection line, 1 bit    
 input s;   
  // output, 32 bits        
output [31:0] y;       
// ternary operator is used so if (s==1) y=a1; else y=a0;    
assign y = s ? a1 : a0;      
endmodule

Now there is also a function facility available in Verilog similar to C language such functions are sections of Verilog code that allow the Digital Designer to write more reusable and maintainable code. Often a function is created when the same operation is done over and over throughout Verilog code. Rather than rewriting code, one can just call the function. This prevents copy and paste errors and allows for more maintainable code: if the behavior of the function changes, it only needs to be updated in one location. One rule about functions is that they cannot have any time delay (# delay, posedge). This is one way in which they differ from tasks. For this reason, functions are used for creating combinational logic. Yes, functions are synthesizable!

Below is a list of rules for functions:

  • Functions can have any number of inputs but only one output (one return value)
  • The order of inputs to a function dictates how it should be wired up when called
  • The return type defaults to one bit unless defined otherwise
  • Functions execute immediately (zero time delay)
  • Functions can call other functions but they cannot call tasks
  • Functions can drive global variables external to the function
  • Variables declared inside a function are local to that function
  • Non-blocking assignment in function is illegal
  • Functions can be automatic 
The following code implements a 32-bit 4-to-1 multiplexer. A 4-to-1 multiplexer selects one input from four inputs and needs a 2-bit selection signal. The assign statement can also be put in above the function block or the below as shown in the below,

2) Multiplexer Using Function:

module mux4to1 (a0,a1,a2,a3,s,y); // 4-to-1 multiplexer, 32-bit
input [31:0] a0, a1, a2, a3; // inputs, 32 bits 
input [1:0] s; // input, 2 bits 
output [31:0] y; // output, 32 bits 
function [31:0] select; // function name (= return value, 32 bits) 
            input [31:0] a0,a1,a2,a3; // notice the order of the input arguments
            input [1:0] s; // notice the order of the input arguments 
            case (s) // cases:
                 2’b00: select = a0; // if (s==0) return value = a0
                 2’b01: select = a1; // if (s==1) return value = a1
                 2’b10: select = a2; // if (s==2) return value = a2 
                 2’b11: select = a3; // if (s==3) return value = a3
            endcase 
endfunction 
assign y = select(a0,a1,a2,a3,s); // call the function with parameters 
endmodule

Thanks For Reading if any doubts write them in the comments I will be giving a reply asap.

Labels:

Comments

Post a Comment

Popular posts from this blog

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...
Post a Comment
Read more

IC Design Engineer at Broadcom

  Hello Dear Readers, Currently, at Broadcom vacancy for an IC Design Engineer role. Job Description: Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc). Should be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis, noise analysis, power optimization. Should be able to implement timing and functional ECOs. Should have excellent problem-solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation. Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Candidate should be able to work independently and guide other team members. Should be ...
Post a Comment
Read more