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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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Multiplexer Verilog Code

Hello Dear Readers,

Here I have giving Verilog code of 32-bit Multiplexer which is a common digital system block. A multiplexer selects an input from multiple inputs. The following code implements a 32-bit 2-to-1 multiplexer as well as a 4-to-1 multiplexer using a function. The [31:0] denotes a bus that has 32 bits. So Let's Start it code.

Verilog Code:

1) Multiplexer Using Dataflow Level:

module mux2to1 (a0,a1,s,y); // multiplexer, 32 bits 
 // inputs, 32 bits
input [31:0] a0, a1;    
  // input selection line, 1 bit    
 input s;   
  // output, 32 bits        
output [31:0] y;       
// ternary operator is used so if (s==1) y=a1; else y=a0;    
assign y = s ? a1 : a0;      
endmodule

Now there is also a function facility available in Verilog similar to C language such functions are sections of Verilog code that allow the Digital Designer to write more reusable and maintainable code. Often a function is created when the same operation is done over and over throughout Verilog code. Rather than rewriting code, one can just call the function. This prevents copy and paste errors and allows for more maintainable code: if the behavior of the function changes, it only needs to be updated in one location. One rule about functions is that they cannot have any time delay (# delay, posedge). This is one way in which they differ from tasks. For this reason, functions are used for creating combinational logic. Yes, functions are synthesizable!

Below is a list of rules for functions:

  • Functions can have any number of inputs but only one output (one return value)
  • The order of inputs to a function dictates how it should be wired up when called
  • The return type defaults to one bit unless defined otherwise
  • Functions execute immediately (zero time delay)
  • Functions can call other functions but they cannot call tasks
  • Functions can drive global variables external to the function
  • Variables declared inside a function are local to that function
  • Non-blocking assignment in function is illegal
  • Functions can be automatic 
The following code implements a 32-bit 4-to-1 multiplexer. A 4-to-1 multiplexer selects one input from four inputs and needs a 2-bit selection signal. The assign statement can also be put in above the function block or the below as shown in the below,

2) Multiplexer Using Function:

module mux4to1 (a0,a1,a2,a3,s,y); // 4-to-1 multiplexer, 32-bit
input [31:0] a0, a1, a2, a3; // inputs, 32 bits 
input [1:0] s; // input, 2 bits 
output [31:0] y; // output, 32 bits 
function [31:0] select; // function name (= return value, 32 bits) 
            input [31:0] a0,a1,a2,a3; // notice the order of the input arguments
            input [1:0] s; // notice the order of the input arguments 
            case (s) // cases:
                 2’b00: select = a0; // if (s==0) return value = a0
                 2’b01: select = a1; // if (s==1) return value = a1
                 2’b10: select = a2; // if (s==2) return value = a2 
                 2’b11: select = a3; // if (s==3) return value = a3
            endcase 
endfunction 
assign y = select(a0,a1,a2,a3,s); // call the function with parameters 
endmodule

Thanks For Reading if any doubts write them in the comments I will be giving a reply asap.

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