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CISC Vs. RISC
Hello Dear Reader,
Most Welcome in my second blog I have started this one after I got succeded in my first blog https://nishitnathwani.blogspot.com/
Today I will be discussing the difference between CISC and RISC two types of hardware systems inside the computer system.
CISC is the general name for CPUs that have a complex instruction set. An instruction set is said to be
complex if there are some instructions that perform complex operations or the instruction formats are
not uniform. The Intel x86 family, Motorola 68000 series, PDP-11, and VAX are examples of CISC.
The CISC instruction set tries to enhance the code density so that a computer system can use a small
amount of memory, including cache, to store as many instructions as possible for reducing the cost and
improving performance.
CISC adopts two measures to reduce the code size – it lets an instruction perform as many operations as
possible and makes the encoding of each instruction as short as possible. The first measure results in using
microcode to implement the complex instructions, and the second measure results in a variable length
of the instruction formats.
As a consequence, it becomes difficult to design and implement a pipelined CISC CPU to obtain substantial performance improvements.
Is every instruction in a CISC complex? The answer is No. There are some very simple instructions in a CISC. The
analysis of the instruction mix generated by CISC compilers shows that about 80% of executed instructions in a typical program uses only 20% of an instruction set and these instructions perform the simple
operations and use only the simple addressing modes.
RISC is the general name for CPUs that have a small number of simple instructions. In the 1980s,
the team headed by David Patterson of the University of California at Berkeley investigated the existing
ISAs proposed the term of RISC and made two CPU prototypes: RISC-I and RISC-II. This concept was
adopted in the designs of Sun Microsystems’ SPARC microprocessors. Meanwhile, the team headed by
John Hennessy of Stanford University did similar research and created MIPS CPUs. Actually, John Cocke
of IBM Research originated the RISC concept in the project IBM 801, initiated in 1974. The first computer to benefit from this project was IBM PC/RT (RISC technology), the ancestor of the RS/6000 series.
There are two main features in a RISC CPU. One is the fixed length of the instruction formats. This
feature makes fetching an instruction in one clock cycle possible. The other feature is the so-called
load/store architecture. It means that only the load and store instructions transfer data between the register
file and memory, and other instructions perform operations on the register operands. This feature makes
the operations of the RISC instructions simple. Both features make the design of the pipelined RISC
CPUs are easier than CISC CPUs. In below Figure is given a short picture summary of this architecture.
The SUN Microsystems SPARC, AMD 29000 family, SGI MIPS, IBM PowerPC, HP PA-RISC, and
ARM are examples of RISC.
Was the CISC replaced by RISC? The answer is No.
The reason is simple – the market. The Intel x86 ISA is widely
used in the IBM-compatible PC, which is the most common computer system in the world. There is a
huge amount of software resources that we cannot throw away.
Today, most CISC CPUs use a decoder to convert CISC instructions into RISC instructions
(micro-operations) and then use RISC cores to execute these instructions. Meanwhile, many RISC CPUs
add more new instructions to support complex operations, multimedia operations, for instance, High-speed signal processing, etc...
Thanks For Reading And Support
Credits:
Computer Principles and Design in Verilog HDL by Yamin Li
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Nice article sir I am waiting your project ideas and Thier verilog code.
ReplyDeleteThanks and yes in short time I will coming with some practical verilog code of my projects as well as others.
ReplyDeleteNice in short summary love from Albania 🤗🤗🤗🤗🤗🤗🤗
ReplyDeleteGood article and keep it up Nishit sir.
ReplyDeleteGood start keep going to make ideal platform.
ReplyDeleteYes I will give my 100 percentage.
DeleteCan you guide how to write verilog code of RISC as well as CISC architecture.
ReplyDeleteProvide VHDL complete series with example will be much useful.
ReplyDeleteSure I will try to complete VHDL series also.
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