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Power Architecture Engineer at Nvidia

Hello Dear Readers,   Currently at Nvidia vacancy for Power Architecture Engineer role. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you’ll be doing: Be part of NVIDIA Power Architecture Group that owns end-to-end power aspects such ...
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CMOS Logic Gates Using Verilog HDL

  CMOS Logic Gate Design 

Hello Dear Readers,

This section describes how to used a low-level CMOS transistor to design basic digital logic gates and its implementation in Verilog HDL.

In CMOS technology, both PMOS as well as NMOS transistors, are used. PMOS is active when the input signal will be 0(Low) level, and NMOS is active when the input signal will be 1(High) level. In below figures show the basic design of the CMOS inverter, NAND, NOR gates. We know if we made AND or OR gate from NAND or NOR respectively, then we need two more transistors of the inverter. That's why we see in the gate array chips contain an array of the universal gates only.




In the below section, I have written the whole Verilog code of all the gates with testbench code.

Verilog Code:

module CMOS_Gates(input a,b,output f,f1,f2
    );
supply1 vdd;
supply0 gnd;
wire w1,w2;

//NOT gate
// pmos (drain, source, gate);
pmos t1 (f, vdd, a);
// nmos (drain, source, gate);
nmos t2 (f, gnd, a);

//NAND gate

// pmos (drain, source, gate);
pmos t3 (f1, vdd, a);
pmos t4 (f1, vdd, b);
// nmos (drain, source, gate);
nmos t5 (f1, w_n, a);
nmos t6 (w1, gnd, b);

//NOR gate

// nmos (drain, source, gate);
nmos t7 (f2, gnd, a);
nmos t8 (f2, gnd, b);
// pmos (drain, source, gate);
pmos t9 (w2, vdd, a);
pmos t10 (f2, w2, b);

endmodule

module tb();
reg a,b;
wire f;
CMOS_Gates DUT (a,b,f,f1,f2);
initial 
begin
   a=0; b=1;
#1 a=1; b=0;
#1 a=0; b=1;
#1 $finish;
end
initial 
begin
$monitor("%2d:\ta = %b\tb=%b\tf = %b\tf1 = %b\tf2 = %b",$time,a,b,f,f1,f2);
end
endmodule
 
Here supply0, supply1, pmos, and nmos are keywords that stand for ground, power supply, PMOS transistor, and NMOS transistor, respectively. Here testbench program is also written with an input signal a,b, and output f,f1,f2 is corresponding to the NOT, NAND, NOR gate.

Thanks for Reading,
If you have any doubts related to this Verilog code, just write them in the comments. I will be giving a reply as soon as possible.



Labels:
Location: India

Comments

  1. Anonymous5 January 2021 at 05:15

    Wow sir great start keep it up.

    ReplyDelete
  2. Unknown6 January 2021 at 04:18

    Good sir now we are waiting project type code🤗🤗🤗🤗🤗🤗🤗

    ReplyDelete
  3. Anonymous9 January 2021 at 19:01

    Nice post

    ReplyDelete

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