Skip to main content

Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
Post a Comment

CMOS Logic Gates Using Verilog HDL

  CMOS Logic Gate Design 

Hello Dear Readers,

This section describes how to used a low-level CMOS transistor to design basic digital logic gates and its implementation in Verilog HDL.

In CMOS technology, both PMOS as well as NMOS transistors, are used. PMOS is active when the input signal will be 0(Low) level, and NMOS is active when the input signal will be 1(High) level. In below figures show the basic design of the CMOS inverter, NAND, NOR gates. We know if we made AND or OR gate from NAND or NOR respectively, then we need two more transistors of the inverter. That's why we see in the gate array chips contain an array of the universal gates only.




In the below section, I have written the whole Verilog code of all the gates with testbench code.

Verilog Code:

module CMOS_Gates(input a,b,output f,f1,f2
    );
supply1 vdd;
supply0 gnd;
wire w1,w2;

//NOT gate
// pmos (drain, source, gate);
pmos t1 (f, vdd, a);
// nmos (drain, source, gate);
nmos t2 (f, gnd, a);

//NAND gate

// pmos (drain, source, gate);
pmos t3 (f1, vdd, a);
pmos t4 (f1, vdd, b);
// nmos (drain, source, gate);
nmos t5 (f1, w_n, a);
nmos t6 (w1, gnd, b);

//NOR gate

// nmos (drain, source, gate);
nmos t7 (f2, gnd, a);
nmos t8 (f2, gnd, b);
// pmos (drain, source, gate);
pmos t9 (w2, vdd, a);
pmos t10 (f2, w2, b);

endmodule

module tb();
reg a,b;
wire f;
CMOS_Gates DUT (a,b,f,f1,f2);
initial 
begin
   a=0; b=1;
#1 a=1; b=0;
#1 a=0; b=1;
#1 $finish;
end
initial 
begin
$monitor("%2d:\ta = %b\tb=%b\tf = %b\tf1 = %b\tf2 = %b",$time,a,b,f,f1,f2);
end
endmodule
 
Here supply0, supply1, pmos, and nmos are keywords that stand for ground, power supply, PMOS transistor, and NMOS transistor, respectively. Here testbench program is also written with an input signal a,b, and output f,f1,f2 is corresponding to the NOT, NAND, NOR gate.

Thanks for Reading,
If you have any doubts related to this Verilog code, just write them in the comments. I will be giving a reply as soon as possible.



Labels:
Location: India

Comments

  1. Anonymous5 January 2021 at 05:15

    Wow sir great start keep it up.

    ReplyDelete
  2. Unknown6 January 2021 at 04:18

    Good sir now we are waiting project type code🤗🤗🤗🤗🤗🤗🤗

    ReplyDelete
  3. Anonymous9 January 2021 at 19:01

    Nice post

    ReplyDelete

Post a Comment

Popular posts from this blog

Best Book for Designing Microarchitecture of Microprocessor Using Verilog HDL

  Hello Dear Readers, Currently, after succeeding in many topics now I starting to provide technical book reviews which were I have completed and still read books always. So let us start today's book review. Book Name:   Computer Principles and Design in Verilog  HDL Description:  Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques...
3 comments
Read more

Internship - SoC /IP Design at NXP India

Hello Dear Readers, Currently, at NXP India  vacancy for  Internship - SoC /IP Design   role.   We are looking for a Master degree student with Electronics and Communication Engineering, or related field, with an emphasis on SoC design. This is a full-time internship with a duration of about 11-12 months. Job Responsibility: Working with our experienced design team to design state of the art SoC hardware specific segment applications like Automotive, IoT, voice/object recognition, security, smart connectivity and touch sensing . Assisting experienced engineers with End-to-end ownership of SoC Design, Verification and implementation (Physical Design). Design and verify digital and Mixed-signal IPs. Document designs and present results. Job Qualification: Master student in electronic/computer engineering Creative and positive mindset Good knowledge on CMOS technologies Great communication skills, interpersonal skills, teamwork skills and can-do attitude Desire for a ca...
Post a Comment
Read more

IC Design Engineer at Broadcom

  Hello Dear Readers, Currently, at Broadcom vacancy for an IC Design Engineer role. Job Description: Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc). Should be able to meet congestion, timing and area metrics.  Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis, noise analysis, power optimization. Should be able to implement timing and functional ECOs. Should have excellent problem-solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation. Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable. Candidate should be able to work independently and guide other team members. Should be ...
Post a Comment
Read more