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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal

What is Simulation? How Simulation Can Guide Real Engineering Design Decisions

 Hello Dear Readers, 

Today in this post I will provide some deep insight into the simulation. So let's start.

Simulation:

Before software tools were developed, the verification of a particular circuit design could only be achieved by the construction of a prototype circuit. While the designer could use standard digital and analog techniques to design the circuit on paper. it was almost impossible to determine whether the circuit would perform as expected in practice. These 'bread boarded' prototype circuits were constructed using discrete components such as individual logic gates, transistors, resistors, capacitors, etc. When built, the circuit would be thoroughly tested and design modifications made on the basis of these tests. The next version of the prototype was then constructed and the process repeated. Such an approach technique was very time-consuming and expensive and resulted in a very long development time. Translation from breadboard to chip often resulted in a different performance owing to different device parameters, different parasitics associated with the circuit, and errors in forming the fabrication mask set.

The solution to the problem is to stimulate the operation of the circuit before the construction of a prototype. Any problem highlighted by the simulation can mean much quicker design iteration and a 'right-first-time' design. The quality of a circuit simulation is critically dependent on two parameters:

  • The simulation routine itself, that is how the mathematical relationships between the signals are implemented and how closely they match the true relationships.
  • How accurately the components that comprise the circuit are modeled.
Simulations can be done at Logic level, Block/Functional or a behavior level. This is called level of abstraction as shown in Fig. 1. Simulator type and associated CPU time is also shown.

Fig. 1: Level of Abstraction


Digital Simulation:
Digital simulation is mostly done at the gate level, while analog simulation is done at the transistor level. True mixed signal simulation is very difficult to perform, partly because of the different level of hieratchy.

In principle, digital simulation is very straightforward: the signal have only two possible states, 1 and 0, and the outputs from the gates are well-defined functions of the inputs. Hence very simple routines can be constructed to predict the output of a circuit based on the conditions of the inputs. Such a simulation is termed a switch-level simulation and can be used to verify the basic functionality of a digital circuit will work in practice. The main problem is the fact that there will be a delay associated with a gate, in that the output will not change concurrently with the input signals. This gate delay may also be dependent on the loading on the gate. The effect of gate delay can result in short erroneous signals on certain nets as an input signal to a gate may change before another, whereas the switch level model predicts they change at the same time. The cumulative effect of the gate delays will put a limit on the overall speed at which the circuit can operate. As well as including time delay information in the model, other features of more advanced gate level simulation include the addition of other signal levels or states. As well as the standard 1,0 and don't care, which can be implemented at the switch level, unknown states can be included. In general, all nets are set at an unknown state at the start of the simulation until such time as the effects of the inputs change them into a known state. This can indicate redundant nets, or be used in fault analysis to identify unexercised nets, as well as checking that the basic functionality is correct. Other signal levels include 'high impedance' where a net is effectively open circuit, for use in tri-state I/O for example. in the below figure 2 show the digital simulation of the arithmetic circuit.

Fig. 2: Digital simulation of the arithmetic and logical unit

Digital simulation is usually done in the time domain. This simulation may be done by taking equal steps in time and analyzing the value of each net after that time period. However, with this approach a small enough time step must be taken to ensure that no short time period transitions are overlooked. Subsequntly there may be comparatively long time periods when no signal changes; the analysis will be repeated many times for no essential reason, thus wasting calculating time. In such cases, the 'event-driven' approach is a better substitute. In this case, any change in a signal triggers a re-analysis of the circuit to see what effect the change has on the connected part of the circuit. Once the effects have been analyzed, the time is advanced until any other signal change is identified; so no unnecessary calculations are made during periods of signal inactivity.

The usual output from a digital simulator is a graphical plot, or corresponding text list, of the signal values on the nets as a function of time. While the true signal voltage varies within the limits of the acceptable logic levels and the transitions between levels take a finite time and are usually of an exponential shape, the plots are at discrete levels, and the transitions are usually shown as instantaneous. The position of the transition, however, is based on the time at which the signal voltage passes the particular logic threshold.

There are many tens of commercial digital simulators, most associated with a particular vendor and usually integrated with a suite of software packages relevant to a particular product. The component libraries are usually modeled on a particular fabrication process; however, the user can edit some parameters such as gate delay, sizing of the transistor, etc...

Analog Simulation:
Analog simulation is potentially much more involved than digital simulation; this is partly due to the greater number of variables and parameters that can be of interest. For example, both time and frequency domain performance can be of interest, and variables can include not only voltages and currents but also noise, gain, input, and output impedance. In addition, component tolerances are of more importance, so sensitivity analysis can be considered. The circuits can be linear and nonlinear in nature, requiring different simulation approaches in each case. Another difference is that it's very difficult to treat analog simulation in the time-discrete way in which event-driven digital analysis is performed. The simulation must be done in a time-continuous way, or at least in a series of discrete time (of frequency) steps of sufficiently small value to model the circuit performance accurately.

Having said that, there is an almost 'standard' approach to analog simulation, which is a time domain, nodel analysis based on the circuit connectivity, as defined by the netlist, and transistor level models of the components of the circuit. A simulator that is based on this approach and that is almost universally used in one form or another is SPICE. As shown in figure 3 the circuit of an CMOS operational amplifier.

Fig. 3: Circuit of CMOS Operational Amplifier

The quasi-time-continuos nodal analysis applied to the transistor level of circuit abstraction can provide solutions to most of the analog simulation problems outlined above. Being nodal analysis for node voltages and the branch current solutions. Frequency domain data; is usually achieved via a discrete mathematical routine known as the Fast Fourier Transform (FFT). Noise analysis can also be incorporated by the inclusion of noise voltage and current sources at the appropriate points. in the analog simulation modeling of the components with accurate thermal dependencies can incorporate temperature effects. most of the modeling things are done in the spice simulation. SPICE ( Simulation Program With Integrated Circuit Emphasis) was developed at the University of California in the mid-1970s and then releases as a public domain software package. SPICE operates at the transistor level of abstraction and can perform DC and AC analysis. DC analysis includes operation points and sweeps DC, while in AC analysis includes a small signal (linear), non-linear, noise simulations, and transient simulations.

The fidelity of these simulations in predicting the true behavior of a real circuit depends upon again the two factors of the mathematical algorithms and the quality of the model both can be extended to improve fidelity. The models for devices such as transistors can be extremely complex but should be based on the physical structure and the behavior of the device. Much work is devoted to the modeling of semiconductor devices to optimize their linear and non-linear behavior.

There are many EDA companies that help the development of semiconductor chips by providing good accuracy of the software packages for the simulations.


 
Image Credits: Ansys, Inc.




Comments

  1. Excellent article on the simulation and everything was perfect and as per expectation.

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