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Physical Design Methodology Engineer at Texas Instruments

  Hello Dear Readers, Texas Instruments Bangalore has a vacancy for the Physical Design Engineer role. We need an Physical Design Methodology Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/SoC chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements: 1 - 2 Years of experience in physical design Bachelor’s or master’s degree in Electrical/Electronics Engineering or a related field Strong understanding of physical design principles Must know the basics of floorplan, placement, CTS, routing, ECO, Physical Verification Proficiency in back-end design tools, such as Cadence Genus/Innovus/Tempus/Voltus Excellent problem-solving skills and attention to detail Effective communication and collaboration skills Responsibilities: Synthesis to GDSII Perform full Physical design flow and its verification Work closely with Digital Design and DFT engineers Ensure...
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ASIC Design Engineer at Juniper Networks

Hello Dear Readers,

Currently, at Juniper Networks Banglore vacancy for an ASIC Design Engineer role.

Job Description:

“This position has the potential to be transferred to Juniper USA after completing one year of employment.  The transfer will be subject to standard transfer eligibility requirements.”

Juniper Development and Innovation (JDI) Silicon Development group is responsible for creating the custom chips that are at the heart of most of Juniper's products. JDI Silicon Team seeks ASIC Engineers to develop next generation of ASICs for new core routers, switches, and firewalls.

  • Our Silicon team delivers on-time and error-free, high-performing, scalable, lowest cost, power efficient Silicon that is widely deployable and beats the competition.
  • ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature-rich without sacrificing in performance. 
  • We have developed 3 generations of high-end router chipsets.

 

JUNIPER Silicon Team works on the latest technologies, currently, we are working on…

  • 7 nanometer
  • 50-100 million placeable objects
  • 500-1000 million gates
  • 10-30B transistors
  • 300 high speed links
  • Clock frequency – 1000- 1300 MHz

 

Job Summary:

Responsible for block level/ full chip design for Custom ASIC’s.

Responsibilities:

  • Responsible for block level/ full chip design.
  • Develop micro-architecture and RTL implementation for ASICs and systems for high-performance networking products.
  • Work with verification engineers to ensure first-time working silicon.
  • Perform logic synthesis and timing analysis.
  • Work with physical design and signal integrity teams to achieve timing closure in routed netlists.


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