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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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ASIC Design Engineer at Juniper Networks

Hello Dear Readers,

Currently, at Juniper Networks Banglore vacancy for an ASIC Design Engineer role.

Job Description:

“This position has the potential to be transferred to Juniper USA after completing one year of employment.  The transfer will be subject to standard transfer eligibility requirements.”

Juniper Development and Innovation (JDI) Silicon Development group is responsible for creating the custom chips that are at the heart of most of Juniper's products. JDI Silicon Team seeks ASIC Engineers to develop next generation of ASICs for new core routers, switches, and firewalls.

  • Our Silicon team delivers on-time and error-free, high-performing, scalable, lowest cost, power efficient Silicon that is widely deployable and beats the competition.
  • ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature-rich without sacrificing in performance. 
  • We have developed 3 generations of high-end router chipsets.

 

JUNIPER Silicon Team works on the latest technologies, currently, we are working on…

  • 7 nanometer
  • 50-100 million placeable objects
  • 500-1000 million gates
  • 10-30B transistors
  • 300 high speed links
  • Clock frequency – 1000- 1300 MHz

 

Job Summary:

Responsible for block level/ full chip design for Custom ASIC’s.

Responsibilities:

  • Responsible for block level/ full chip design.
  • Develop micro-architecture and RTL implementation for ASICs and systems for high-performance networking products.
  • Work with verification engineers to ensure first-time working silicon.
  • Perform logic synthesis and timing analysis.
  • Work with physical design and signal integrity teams to achieve timing closure in routed netlists.


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