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RTL Design Engineer at Skyroot Aerospace

Hello, Dear Readers, Skyroot Aerospace has a vacancy for the RTL Design Engineer role. About Skyroot Aerospace: A cutting-edge startup founded by ex-ISRO scientists. Dedicated to affordable space access, we're rewriting aerospace technology rules. Our dynamic team fosters inventiveness, collaboration, and relentless excellence. Join us on a transformative journey to redefine space possibilities. Welcome to the forefront of space innovation with Skyroot Aerospace! Purpose of role: Understand architectural requirements and Design micro-architecture, implement design blocks using VHDL/Verilog for FPGA based Avionics packages for orbital launch vehicles and ground infrastructure. Job Requirements: 2+ Years of RTL and system design experience. Strong knowledge on Digital System Design (DSD). Strong knowledge of RTL/SoC design/integration with VHDL/Verilog. Strong knowledge in problem solving and debugging skills. Ability to understand architectural requirements and Design micro-archite...
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ASIC Design Engineer at Juniper Networks

Hello Dear Readers,

Currently, at Juniper Networks Banglore vacancy for an ASIC Design Engineer role.

Job Description:

“This position has the potential to be transferred to Juniper USA after completing one year of employment.  The transfer will be subject to standard transfer eligibility requirements.”

Juniper Development and Innovation (JDI) Silicon Development group is responsible for creating the custom chips that are at the heart of most of Juniper's products. JDI Silicon Team seeks ASIC Engineers to develop next generation of ASICs for new core routers, switches, and firewalls.

  • Our Silicon team delivers on-time and error-free, high-performing, scalable, lowest cost, power efficient Silicon that is widely deployable and beats the competition.
  • ASIC is the differentiator starting from our 1st router to our latest products. Our ASIC’s have been feature-rich without sacrificing in performance. 
  • We have developed 3 generations of high-end router chipsets.

 

JUNIPER Silicon Team works on the latest technologies, currently, we are working on…

  • 7 nanometer
  • 50-100 million placeable objects
  • 500-1000 million gates
  • 10-30B transistors
  • 300 high speed links
  • Clock frequency – 1000- 1300 MHz

 

Job Summary:

Responsible for block level/ full chip design for Custom ASIC’s.

Responsibilities:

  • Responsible for block level/ full chip design.
  • Develop micro-architecture and RTL implementation for ASICs and systems for high-performance networking products.
  • Work with verification engineers to ensure first-time working silicon.
  • Perform logic synthesis and timing analysis.
  • Work with physical design and signal integrity teams to achieve timing closure in routed netlists.


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