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Design Engineer - STA, SD, Power, PDN at Dew Software

Hello Dear Readers,   Currently at Dew Software Bangalore vacancy for Design Engineer - STA, SD, Power, PDN role. Dew Software, a leading player in the Digital Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation strategies, the Design Engineer will be responsible for ensuring the integrity and efficiency of digital designs through comprehensive analysis and optimization. Dew Software is dedicated to delivering exceptional outcomes with cutting-edge technologies, and this is an excellent opportunity to contribute to the growth and success of our clients. Responsibilities: Perform STA (Static Timing Analysis) to ensure design meets timing requirements Conduct signal integrity analysis to optimize signal integrity and minimize signal integrity issues Provide power anal
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RTL Front End Design Engineers at Wafer Space Bangalore

Hello Dear Readers,

Currently, at Wafer Space Bangalore vacancy for an RTL Front End Design Engineers role.

Job Responsibilities:

  • Chip integration of high complexity SOCs.
  • Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
  • Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
  • Formal Verification between RTL to Netlist and Netlist to Netlist
  • Manual and Conformal ECO
  • Running Lint (Spyglass) at SoC level.
  • Chip-level integration and connectivity.
  • Debugging FV failures
  • ECO implementation.


Desired Skills and Experience:

  • 2 - 10 years of experience
  • Sound knowledge in Micro Architecture design and RTL implementation
  • Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs, and mobile SOCs is desirable
  • Experience in Synthesis and pre-layout timing analysis
  • Understanding of DFT flow is desirable
  • Experiencing using clear case a must
  • Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
  • Proficiency in LEC and formal flows.
  • Experience in Perl, TCL, and shell scripting
  • Excellent interpersonal & analytical skills with the ability to work independently

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