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Engineer I at SiFive

Hello Dear Readers,   Currently at SiFive vacancy for Engineer I role . As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. Job Description:   Responsibilities: Engage in the logic design and verification of digital IPs, CPUs, peripherals, and sub-systems across various VLSI domains. Create and implement innovative designs and testbenches that are highly scalable, configurable, and efficient. Strong hands-on experience with UVM testbench devel...
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RTL Front End Design Engineers at Wafer Space Bangalore

Hello Dear Readers,

Currently, at Wafer Space Bangalore vacancy for an RTL Front End Design Engineers role.

Job Responsibilities:

  • Chip integration of high complexity SOCs.
  • Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
  • Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
  • Formal Verification between RTL to Netlist and Netlist to Netlist
  • Manual and Conformal ECO
  • Running Lint (Spyglass) at SoC level.
  • Chip-level integration and connectivity.
  • Debugging FV failures
  • ECO implementation.


Desired Skills and Experience:

  • 2 - 10 years of experience
  • Sound knowledge in Micro Architecture design and RTL implementation
  • Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs, and mobile SOCs is desirable
  • Experience in Synthesis and pre-layout timing analysis
  • Understanding of DFT flow is desirable
  • Experiencing using clear case a must
  • Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
  • Proficiency in LEC and formal flows.
  • Experience in Perl, TCL, and shell scripting
  • Excellent interpersonal & analytical skills with the ability to work independently

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