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VLSI Packaging Evolution and Innovations

Hello Dear Readers,   Today in this post, I will provide some deep insight into the VLSI packaging evolution and innovations. Semiconductor packaging has evolved from a simple protective housing into a critical performance enabler. In the modern VLSI landscape, packaging is no longer an afterthought; it is a fundamental determinant of PPA (Power, Performance, and Area) metrics, often dictating the thermal limits and signal integrity of the final SoC. 1. Traditional Packaging Technologies: These methods are the workhorses of the industry, widely used for low-to-medium complexity devices where cost-efficiency is paramount. Wire Bonding (QFN, QFP, DIP): Wire bonding is the most mature interconnection technology. It uses thin gold, copper, or aluminum wires to connect the die's bond pads to the package's internal leadframe. Implementation: The die is attached face-up to a leadframe or substrate. A wire bonder uses thermocompression or ultrasonic energy to attach wires betwee...

Intern - Design & Technology Enablement at Global Foundries

 Hello Dear Readers, 

Currently at Global Foundries vacancy for an Intern - Design & Technology Enablement role.

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets.

Introduction:

As part of the PDK infrastructure group, the candidate will contribute to the software development of Process Design Kits and Design Manual infrastructure efficiency and innovation projects.

Your Job:

  • Contribute to the development and testing of PDK infrastructure group
  • Propose and develop software-based solutions for technical needs
  • Communicate with the team to understand the requirements and report status

Other Responsibilities: 

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements, and programs

Required Qualifications:

  • Education – Actively pursuing a master’s or PhD in software development or related field. 
  • Language Fluency - English (Written & Verbal) 
  • Ability to work at least insert hours: 20 hours per week during the internship.
  • Knowledge of at least two of the following:
    • Linux, shell scripting, and server maintaining processes
    • Frontend development with Vue.js
    • Python development
    • Oracle Database
    • Java/Java script

Preferred Qualifications:

  • Prior related internship or co-op experience
  • Project management skills, i.e., the ability to innovate and execute solutions that matter; the ability to navigate ambiguity. 
  • Strong written and verbal communication skills 
  • Strong planning & organizational skills
  • Experience in Angular or React frameworks
  • Knowledge of machine learning and AI algorithms

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