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Hello Dear Readers,
Today in this post I will provide some deep insight into what is happening in the semiconductor industry. So I hope you like it and enjoy it to improve your knowledge and awareness about the industry. So let's start it today we are discussing, The Importance of 3D IC Ecosystem Collaboration in the VLSI Market.
As design teams continue to develop new generations of transformative products, the demand for computing remains relentless. Modern workloads have brought packaging technologies to the forefront for innovation and pushed the boundaries for silicon product design in terms of product performance, function and cost. Not too long ago, packaging technologies were thought of as inconvenient back-end processes. But times have changed, and rising advancements in artificial intelligence, big data, cloud computing, and autonomous vehicles have pushed the computing envelope unlike ever before (along with the need for packaging technologies).
This computing evolution has resulted in the shrinking of chips and the emergence of multi-die architectures, creating a promising landscape for 3D silicon stacking and advanced packaging innovation for optimized system performance. 3D ICs offer a practical way to promise a whole new level of power, performance, area and functionality.
However, the right choice of packaging depends on many factors, and designers need help navigating the best path through the myriad options and approaches available. To speed up the adoption and production of future 3D ICs, the semiconductor industry needs a streamlined, collaborative ecosystem that can provide best-in-class optimization at the system level.
Looking closely at 3D silicon stacking:
Traditionally, key players in the semiconductor industry, such as EDA, IP, substrate, memory and testing vendors, would focus on one pillar of expertise — without gaining a deep understanding of how their work affected the chip’s overall integration and compatibility. This meant that teams would not only use different tools on the front end but would need a joint product roadmap and well-defined communication channels among all parties involved. Such fundamental front-end and back-end inefficiencies increased design complexity, requiring more collaboration between players to reduce late integration, increase productivity levels and strengthen system product innovation.
In terms of the stacking itself, packing multiple layers of transistors on differently sized chips requires the utmost precision. Unlike in the past, when teams could desolder a faulty chip on a printed-circuit board and replace it with a new chip at the system-testing stage (even if stacked), teams cannot access chips once assembled in a 3D IC structure. In the event that an error occurs, the chip needs to be tossed and created again.
Say a foundry releases a new design update to its customer. By the time the customer receives the update and releases it to its IP vendors, meaningful time is lost. Adding fuel to the fire, it takes about six months to a year for the corresponding IP to be ready. During this process, should the respective EDA vendor not be aware of the foundry’s latest design rule, the EDA tool ends up being invalid for the latest design update — a difficult situation for everyone involved.
EDA tools rely on interoperability and need to have complete, end-to-end tools for effective 3D multi-die system integration. While this may have been relatively easy to cater to single-chip designs, both the interaction between chips stacked on top of each other in a 3D IC architecture and for the EDA tool to recognize whether a chip is 3D-stacked isn’t as straightforward.
Accelerating design success:
Leveraging advanced packaging technologies for heterogenous chip integration has been a clear trend for many applications. With continuing growth of compute-intensive applications across different industries, 3D IC is enabling innovation for HPC, automotive, IoT and mobile use cases.
Domain-specific chiplets offer the industry incredible value, though they require advanced packaging for teams to have enough options to stack wafers on wafers or chips on wafers to gain higher density, greater functionality and better performance — all while keeping the same or smaller footprint.
This opportunity widens the possibilities for the industry to advance while navigating increasing chip complexity and design sizes. Irrespective of whether a vendor changes their business model, the integration and packaging of chiplets with multiple layers, multiple chip sizes and multiple functions will be of paramount importance to unlock ultimate design flexibility with high compute power and small form factors.
As a comprehensive family of 3D silicon stacking and advanced packaging technologies, TSMC 3DFabric complements the company’s advanced semiconductor technologies to unleash system-level innovations. Our front-end technologies, or TSMC-SoIC (system on integrated chip), offer the precision and methodologies needed for today’s 3D silicon stacking requirements.
To that end, TSMC customers have a unique outlook when it comes to tackling compute hurdles.
AMD, a pioneer in 3D silicon stacking, is one such customer that has benefited from tremendous performance improvements. The company spearheaded the world’s first TSMC-SoIC–based CPUs by working with TSMC and its Open Innovation Platform (OIP) partners, accelerating the development of a robust chiplet-stacking ecosystem for future generations of high-performance, energy-efficient chips.
Transforming collaboration:
No customer or partner can singlehandedly enable system-level innovation at the scale that is needed. Effective collaboration across all chip companies, design partners and foundries in the ecosystem (EDA, IP, DCA/VCA, memory, OSAT, substrate and testing) will be critical to unleash the next step for system integration and product innovation.
Recognizing the need to accelerate 3D IC ecosystem innovation and streamline execution, TSMC launched the TSMC 3DFabric Alliance in October 2022 as part of the existing TSMC OIP. Customers and design companies can now gain access to the platform to collaborate on best-in-class 3D IC solutions and get designs right the first time with clearer product roadmaps.
This empowers the wider ecosystem to develop better-quality 3D IC system designs and achieve faster time to market compared with designing larger monolithic dies — eventually vastly accelerating 3D IC customer adoption and ecosystem readiness.
As workloads evolve, it is important for packaging technologies and semiconductors to progress together. The birth of such collaborative initiatives sets the stage for a new and viable era that can handle complex process nodes and provide advanced 3D IC design solutions for a variety of applications and fields.
Going forward, TSMC expects to see a shift from companies focusing solely on designing chips to implementing a holistic, well-rounded approach around system-level integration to bring a new level of product innovation alive. In the meantime, we will continue to make every effort to open new doors for the industry to continue to innovate in this promising space.
The Founding of 3DFabric Alliance Partners:
The formation of this new alliance further cements relationships with current and new OIP partners while addressing immediate customer needs and providing a set of forward-looking enhancements and solutions for our mutual customers’ innovative 3D IC system designs in a variety of applications and fields. TSMC has categorized our partners as follows: EDA, IP, DCA/VCA, Memory, OSAT (Outsourced Semiconductor Assembly and Test), Substrate, and Testing.
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| Source: https://www.tsmc.com/english/news-events/blog-article-20221108 |
Ansys & Synopsys:
Power, Thermal, and Reliability Signoff of Advanced SoCs, 2.5D and 3DIC:
The design challenges that have emerged at 7nm and below, as well as with huge 2.5D/3D systems, can no longer be addressed as an afterthought at the very end of the design cycle. A range of novel physical effects, from thermal analysis to electromagnetic interference and advanced 3D layout capabilities, need to inform the design right from the prototyping stage. To deliver the industry’s best EDA solution for these new challenges, Ansys and Synopsys have entered into a strategic alliance that builds on the companies’ foundry-certified golden signoff technologies. Ansys’ RedHawk-SC™ family of industry-leading power integrity, thermal, and reliability signoff products have been integrated with Synopsys' best-in-class Fusion Compiler™ platform, 3DIC Compiler™ platform, and PrimeTime® signoff platform to provide customers golden signoff accuracy for chip, package, and system-level effects within the Synopsys design environment. This enables a faster, shift-left methodology with rapid design exploration, early weakness detection, in-design analysis, voltage-timing optimization, thermal-aware reliability, and final signoff from within the place-and-route environment.
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| Source: https://www.synopsys.com/partners/ansys.html |
Cadence:
The Cadence Integrity™ 3D-IC Platform is the new high-capacity, unified design and analysis platform for designing multiple chiplets. Built on the infrastructure of Cadence’s leading digital implementation solution, the Innovus™ Implementation System, the platform allows system-level designers to plan, implement, and analyze any type of stacked die system for a variety of packaging styles (2.5D or 3D). Integrity 3D-IC is the industry’s first integrated system- and SoC-level solution that enables system analysis, including co-design, with Cadence’s Virtuoso and Allegro analog and package implementation environments.
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| Source: https://www.cadence.com/content |
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