Skip to main content

Senior Eng CAD Engineering at Global Foundries

Hello Dear Readers,   Currently at Global Foundries, vacancy for Senior Eng CAD Engineering role. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Technology Computer Aided Design tools are critical to accelerate the technology development and deployment in our Fabs. We are seeking to strengthen our TCAD team with highly motivated Individuals who are at the early phase of their career. The candidate brings passion for semiconductor technologies and devices, strives for high-quality work, cares about details, and is willing to learn and cooperate in a...
Post a Comment

RTL Design Engineer at OpenFive

 Hello Dear Readers,

Currently, at OpenFive vacancy for RTL Design Engineer role.

OpenFive is looking for an individual with strong RTL Design skills. The SOC IP Team is responsible for all in-house soft and hard IPs. As an employee, you will have the opportunity to work on any of the IPs in our portfolio, which are as follows:

  •  100G/400G Ethernet
  • Memory Controllers and Soft PHYs
  • High Throughput/Low Latency Interlaken Controllers
  • D2D Controllers

We are a team with soft boundaries across teams and it is possible for you to work on one or more of these IPs from time to time. You would also get the opportunity to work on these IPs targeted for the latest tech nodes from different foundries Ex 5nm, 7nm etc. We also tapeout test-chips on a regular basis to prove our IPs in Silicon. This provides an excellent opportunity for you to learn the entire tapeout process and post-silicon validation as well.
Our Team focuses on high-quality of work and strong work ethic! We have a very exciting workplace and look forward to having you on-board.
The job profile involves the following at broad level and depending on the grade you are hired for you will get to work on various aspects of the job profile.
 
Our workplace provides an excellent opportunity to enhance your skill set not only in RTL Design and Verification but an all-round perspective:

  • Understanding of the IP marketplace
  • View into the overall semiconductor industry trends
  • Development of Industry Standard requirements and thus better Design/Verification ethics

 

Responsibilities:

  • Will be given an independent block(s) in an IP to be owned end-to-end which includes Microarch development, RTL design, review of Verification plan and full debug support
  • Required to support Emulation activities as well
  • Will need to guide juniors technically.
  • Interface with customers on various deliverables

Requirements:

  • Minimum 2 years of experience in RTL Design
  • Candidate must have Worked on RTL design of major blocks
  • Worked on micro-arch of major blocks
  • Strong knowledge in Design (Verilog) and verification aspects of design
  • Experienced at least one complete delivery from start to finish
  • Good analytical and Debug skills
  • Good knowledge in at least one/two of these protocols
  • HBM or DDR , Ethernet, Interlaken, AMBA
  • Expected to have very deep knowledge/understanding on the blocks that you have worked on
Labels:

Comments

Post a Comment

Popular posts from this blog

Exploring the Role of LEF Files in VLSI Chip Design: A Beginner's Guide

Hello Dear Readers,   Today in this post, I will provide some deep insight into the LEF file role during the VLSI Chip Design process. In VLSI (Very Large Scale Integration) design, a LEF file is a file that contains information about the physical geometry of the standard cells used in a circuit. LEF stands for Library Exchange Format. A standard cell is a pre-designed logic cell that contains a specific function, such as a flip-flop or an AND gate. Standard cells are designed to be easily combinable and scalable to create more complex circuits. The physical geometry of each standard cell is defined in the LEF file. The LEF file contains information such as the width, height, and position of the pins and metal layers of each standard cell. It also contains information about the physical design rules that govern the placement of these cells on the chip. LEF files are important in VLSI design because they enable the interoperability of different design tools from different vend...
4 comments
Read more

Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes

  Hello Dear Readers,   Today in this post, I will provide some deep insight into the Signal Electromigration (Signal EM): Violations, Examples, and Practical Fixes. 1. Introduction: As technology nodes shrink into the deep‑submicron and nanometer regime (7nm, 5nm, 3nm and beyond), electromigration (EM) has become a first‑order reliability concern—not only for power/ground (PG) networks but also for signal nets. Signal EM failures are often underestimated because signal currents are transient and bidirectional. However, with higher switching activity, tighter metal pitches, thinner wires, and aggressive timing closure, signal EM can cause latent or early‑life failures if not addressed properly. This article explains: What Signal EM is and how it differs from PG EM Typical Signal EM violation scenarios Detailed, practical examples Root causes behind each violation Proven solutions and best practices to fix and prevent Signal EM issues 2. What is Signal Electromigration: El...
Post a Comment
Read more

Physical Design/PDK methodology Engineer

Hello Dear Readers, At Applied Materials Bangalore, there is a vacancy for a Physical Design/PDK methodology Engineer role. Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips – the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world – like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world.  Key Responsibility: Expertise in PDK enablement and library  validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and ...
1 comment
Read more