Hello Dear Readers,
Currently, InnoPhase Bangalore has a vacancy for a VLSI Digital Design Engineer role.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
As a VLSI Design Engineer, you will be collaborating with a team of design engineers to develop novel ORAN SoC products for high-performance applications such as LTE and sub-6 GHz 5G cellular base stations. You will also be contributing to functional block design and integration to meet detailed device performance requirements. This role is an excellent opportunity for someone that enjoys learning and making a significant impact in launching products into the market and winning! This position can be based in Bangalore, India.
Key Responsibilities:
- Participate in SoC specifications reviews and contribute to micro-architecture definitions
- Front-end digital design and implementation – RTL coding, CDC, Lint, and synthesis
- Develop design constraints and coordinate to debug both functional and DFT test issues
- Help to improve SoC design methodologies and verification quality
- Support IP/Design Verification/Firmware/Software System/Production teams to provide the necessary support for the timely closure of assigned blocks design and implementation issues
Job Requirements:
- BS/MS EE/CS with relevant VLSI coursework
- Good understanding in RTL design and simulation using Verilog/SystemVerilog/VHDL
- Good understanding of front-end design from RTL to gate level synthesis
- Good understanding on back-end design flow on logic synthesis, constraints, timing analysis, DFT
- Knowledge of SystemVerilog assertions, checkers, and other design verification techniques
- Knowledge of languages such as C/C++, Perl, Tcl and Python
- Team player with the ability to collaborate with cross-functional teams to resolve issues effectively
Desirable Skills:
- VLSI design with RTL coding & simulation in Verilog/SystemVerilog/VHDL
- Experience in Python or Perl scripting for verification automation and report generation
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