Finite State Machine (FSM) Modelling Using Verilog HDL

Hello Dear Readers,

Today, I will explain how Finite State Machine (FSM) is modeling using Verilog HDL.

The finite state machine (FSM) is a very important design block in the ASIC design. Most of the ASIC designs and controller design needs efficient and synthesizable state machines and are commonly called FSM. The FSMs can be described very efficiently by using the Verilog HDL and for ASIC design engineers.

Basically, FSMs are predefined sequences on the preordered or defined events and are source synchronous designs. FSMs can be coded efficiently for the synthesizable outcome using the multiple- or single-procedural block. In the practical scenario, it is recommended to use the multiple-procedural blocks to describe the state machines. One of the procedural blocks can describe the combinational logic and level-sensitive to the inputs or the states. Whereas, the other procedural block can be edge sensitive to the positive edge of the clock or to the negative edge of the clock.

1). State machine types:

i). Moore -vs- Mealy:

A Moore state machine is classified as an FSM where the outputs are only a function of the present state, while Mealy state machines have one or more outputs that are a function of the present state and one or more FSM inputs.

Fig.1 - Moore & Mealy State Machine block diagram

Moore state machines are favored in industry because the outputs have a full cycle to settle through the combinatorial logic and are therefore easier to meet required cycle times. Mealy outputs allow an input to appear after the cycle has started, and the input must still traverse the combinatorial logic and meet setup time for the Mealy output. If the design absolutely requires an input to make it on‐ chip after the active clock edge, pass through logic and appear on the output all within one cycle, those are the designs that typically use a Mealy output.

The timing analysis for the Moore machine is very simple due to clean register-to-register path but for the Mealy machine there might be chances of timing violations if the input changes during the setup time window. But the disadvantage of the Moore machine is it needs more states compared to the Mealy machine. The practical scenario is that the Mealy machine has one state less compared to the Moore machine.

ii). Binary -vs- OneHot encoding:

The second major classification is whether the state encoding of the FSM designs are binary (also referred to as highly encoded) or if they are OneHot. There are multiple binary encoded styles but what they have in common is that they typically use fewer flip‐flops to create unique binary encodings for each state in the FSM design than OneHot FSM designs. OneHot encoding uses one flip‐flop for each state in the state machine and when the state machine is in that state, that flip‐flop is "hot" or equal to "1" while the rest of the states are equal to "0." Since transitioning from one state to another only requires that the previous hot flip‐flop be set to 0 and the new hot flip‐flop be set to 1, the combinatorial logic to transition between states is typically very simple. OneHot FSM designs are typically inferred automatically by FPGA synthesis tools.

Fig.2 Binary -vs- OneHot state diagrams

2). FSM Encoding Styles:
FSM can be described by many styles and practically there are three encoding styles used to describe the FSMs. These styles are named as

i). Binary Encoding:  

g FSM can be described by using binary encoding styles and by using this style, the number of register elements used is equal to the log(number of states) 2 base. Consider an FSM has four states; then, the number of registers equal to log4(base 2) is equal to 2.

ii). Gray Encoding: 

FSM can be efficiently described by using the Gray encoding technique and in this style, the gray codes are used to represent the states. The number of register elements used is equal to log( number of states) 2 base. Consider an FSM has four states; then, the number of registers equal to log4(base 2) is equal to 2.

iii). One-hot Encoding: 

g FSMs can be efficiently described using a one-hot encoding style. One-hot indicates that only one bit is active high at a time or hot at a time. The number of register elements used is equal to the number of states in the FSM. Consider an FSM has four states than the number of registers also equals 4. This style requires more area but the advantage is it has a clean register-to-register path and it makes STA very simple. If FSM has 16 states then one-hot encoding needs 16 flip-flops. So let's start modeling FSM of level to pulse converter.

The level to pulse converter partial state transition diagram is shown in Fig.3. As shown in the diagram the FSM remains in the state ‘S0’ for the input data_in=0 and for the data input data_in=1, it remains in the state ‘S1.’ The state transition table for the Mealy level to pulse converter is shown in Fig.4.

Fig.3 http://courses.csail.mit.edu/

Fig.4 http://courses.csail.mit.edu/

3). Verilog Code:

module levelTopulse(data_in,clk,rst,y_out);
input data_in,clk,rst;
output reg y_out;
parameter s0=0,s1=1;
reg current_state,next_state;
// state logic definition
always @(posedge clk or negedge rst)
begin
  if(~rst)
     current_state<=s0;
else
     current_state<=next_state;
end
// next state logic definition
always @(data_in or current_state)
begin
case (current_state)
s0:begin if(data_in) next_state=s1;
         else next_state=s0;
end
s1:begin if(data_in) next_state=s1;
         else next_state=s0;
end
default: next_state=s0;
endcase
end
//output logic definition
always @(current_state,data_in)
begin
case(current_state)
s0:begin if(data_in) y_out=1'b1;
         else y_out=1'b0;
end
s1:y_out=1'b0;
default: y_out=1'b0;
endcase
end
endmodule

4). Simulational Results:

5). Layout of FSM:

Here RTL to GDSII flow is implemented in Qflow using OSU180nm technology node shown in Fig.5.

Fig.5  Final Layout of Level to Pulse converter

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